Translation of "Abfallenden flanke" in English

The integrator INT is stopped at the point of time of the trailing edge of the envelope.

In the further course of the falling edge of the phase, the sets of LEDs are successively disabled.

After switching of a comparator, deintegration to generate the falling flank occurs.

The switch 12 a then switches on again, with the falling edge.

These are located on the descending curve of the total current and can have a positive or negative sign.

The monoflop is thus triggered by each leading and trailing edge of each pulse.

The addresses are read in with the trailing edge of the chip-enable signal and are forwarded to the address decoder.

Thus, an output signal is generated comparatively quickly after the beginning of the positive-going or negative-going edge of the input signal.

Now a pressure drop is produced which corresponds to the descending flank 31 in the curve 3 .

At this moment the received line synchronizing pulse H coincides with the falling edge of Uz.

At first, the line synchronizing impulses H do not coincide with a falling edge 2 of Uz.

At t2 the coinciding of the falling edge 3 of Uz with the line synchronizing pulse H1 is established.

On occurrence of a falling flank S- 52 F of the signals S- 52, this second counter is reset.

During the falling edge of the voltage waveform, the sets of LEDs may for instance be disabled in the reverse order.

The peak results from the switching element T 1 switching on during the steeply falling edge of the output voltage pulse.

This noise compensation can also be carried out at the rear or falling flank of the signal pulse 15 .

Thereby the light can be emitted and/or incident into the region of the flank 13 b .

Preferably around 5 to 10 pulses should occur within the rising or the falling edge of the curve.

The rising edge of the pulse assigned to the scavenging agrees with the decaying edge of the pulses for coil 4.

The rising edge of the pulses assigned to the scaling agrees with the decaying edge of every other scavenging pulse.

The D-flip-flop FF32 in the second switching network SN2 is allocated t the input clock signal sequence CL2 now selected. It is initialized via its data input D and is set at point in time t14 with the next-following, trailing edge of the input clock signal sequence CL2 which is now selected.

Once the pump pistons have rolled off on the descending flank 62 and entered a detent 69 of the cam race, the second electrically controlled valve 46 is then opened, as shown in FIG. 4d.

The correction signal K subsequently appears, causing the control signal Stx to be disconnected at point in time t4 at the next trailing edge of the clock Tx. The control signal Stx+1 is engaged at point in time t5 with the next trailing edge of the clock Tx+1.

The transit time t between the last trailing edge of the clock Tx and the point in time t4 thus has no influence on the auxiliary data clock DHT until point in time t4 encounters the next, leading edge of the clock Tx.

The time span that is critical for the access time is the time from the trailing edge of the chip-enable signal up to the trailing edge of one of the two output signals.

On the falling flank of the cam track 15, against which the roller shaft 21 rests, the corresponding pump piston 20 in FIG.

If this time is smaller than limit value G, then no problem S is indicated whereupon the time monitoring function is reset to the initial state and started again with the next descending edge 82 of driver current ID.

In order to set the relative movement between driver pin 52 and recess 39, a ramp-like step 54, 55 is provided ahead of the end 41b, 42b of each of the two cam segments 41, 42 in recess 39 (FIG. 6), said ramp-like step 54, 55 rising evenly from the groove base 56, then finishing with a flank 57, 68 dropping perpendicularly to groove base 56.

The detent pawl is raised by one flank of the toothed structure, and after passing the descending flank, drops under gravity into the gaps between the teeth.