Übersetzung für "Complementary mos" in Deutsch

The electronic switches are preferably complementary MOS-FETs.

The MOS transistors and the complementary MOS transistors are each realized as a vertical layer sequence.

A realization in single as well as in complementary MOS technology is also possible.

The current mirror arrangement is preferably constructed using complementary MOS circuit technology.

In other words the CBi semiconductor device has at least one MOS semiconductor component or complementary MOS semiconductor components.

The invention relates further to a method of producing a large-scale integrated complementary MOS field-effect transistor circuit (CMOS circuit).

The two complementary MOS transistors are controlled by input signals that are inverses of one another, each conducting or blocking simultaneously.

Consequently, the definitive countervailing duties paid or entered in the accounts pursuant to Council Regulation (EC) No 1480/2003 on imports of certain electronic integrated circuits known as Dynamic Random Access Memories (DRAMs) manufactured using variations of metal oxide-semiconductors (MOS) process technology, including complementary MOS types (CMOS), of all types, densities, variations, access speed, configuration, package or frame etc., originating in the Republic of Korea and released for free circulation as from 31 December 2007 should be repaid or remitted.

The countervailing duty imposed on imports of certain electronic integrated circuits known as Dynamic Random Access Memories (DRAMs) manufactured using variations of metal oxide-semiconductors (MOS) process technology, including complementary MOS types (CMOS), of all types, densities, variations, access speed, configuration, package or frame etc. originating in the Republic of Korea imposed by Regulation (EC) No 1480/2003 is repealed as of 31 December 2007 and the proceeding is terminated.

The gates of these two complementary MOS-transistors of the individual inverter together form the signal input of the inverter, while its signal output is represented by a circuit point between the series-connected source-drain paths of the two transistors of the inverter.

The replacement of the flip-flops which are customarily used as comparators and are equipped exclusively with transistors of the type of the transistors used in the single-transistor memory cells, by a comparator constructed in complementary MOS-technology, obviously requires an increase of the technical effort provided in the manufacture of the memory matrix.

Prior Art Workers in the art are aware of processes for manufacturing highly integrated complementary MOS field effect transistor circuits (CMOS-FET's) wherein different technologies, which are very involved, are utilized for source/drain implantation of n-channel and p-channel transistors.

The present patent application relates to a method for manufacturing VLSI complementary MOS-field effect transistor circuits (CMOS circuits), wherein p-doped or n-doped tubs are generated in the silicon substrate for the acceptance of the n-channel or p-channel transistors of the circuit. The corresponding dopant atoms are introduced into the tubs by means of multiple ion implantations for the purpose of setting the various transistor threshold voltages. The masking for the individual ion implantations occurs by means of photosensitive resist, silicon oxide, or silicon nitride structures, and the manufacture of the source/drain regions and gate regions as well as the generation of the intermediate and insulating oxide and of the interconnect level is undertaken according to known method steps of MOS technology.

BACKGROUND OF THE INVENTION Field of the Invention The present invention is directed to a circuit containing integrated bipolar and complementary MOS transistors on a common substrate wherein suitably doped wells are provided in the substrate for accepting p-channel or n-channel transistors, the wells forming the collector of the bipolar transistor.

In integrated circuits of this species in complementary MOS technology, parasitic pnpn paths between the supply voltage and the ground occur that are similar to a thyristor.

In integrated circuits of this species in complementary MOS technology, parasitic pnpn paths between the supply voltage (VDD) and the ground (Vss) occur that are similar to a thyristor.

This is caused by the fact that the complementary MOS-transistors in the switch are correctly brought into the conducting condition by a positive bias, that however the change into their blocked condition is performed only by dropping this bias.

Heretofore known solutions of the last-mentioned problems are based upon the use of inverters constructed from complementary MOS transistors.

However, with a transfer of these process steps into the manufacture of complementary MOS field effect transistor circuits (CMOS circuits) difficulties arise because a rounding of the rims and edges in the contact hole areas can only be performed before the etching of the contact holes. Otherwise, the p+ regions would be uncovered and a depletion of doping materials would occur in these regions due to the applied high temperature.

In comparison to the method described in European Patent Application No. 0 101 000, the method of the present invention has the advantage of simultaneous manufacture of complementary MOS (CMOS) transistors with bipolar transistors being generated in the n-wells and having buried n+ -doped zones and deep collector terminals annularly placed into the wells, thus resulting in a reduction of the collector series resistance as well as an increased latch-up hardness of the circuit.

An embodiment of a static memory cell according to the present invention includes two complementary transistors, preferably MOS field effect transistors ("MOSFETs"), which can be connected directly, with positive feedback, without additional components, so that the drain output of each transistor is directly connected with the source input of the other transistor.