Translation of "Memory subsystem" in German

Disk Memory Subsystem 3 is sometimes referred to as volume cache in the description.

The output of the pixel pipeline 20 is connected to a memory subsystem 24 via a packing unit 22 .

The memory subsystem 24 can either read or write such a word during a clock cycle.

The memory subsystem 24 typically manages so-called memory words containing a plurality of pixels.

Examine my memory subsystem next.

The tones are generated by a subsystem 6 with a subsystem computer UMC which comprises a subsystem memory URAM and a subsystem microprocessor UCPU.

A bus switch BS is designed to alternately connect the memory bus SB, which leads to subsystem memory URAM, with the main system bus HB and with a subsystem bus UB.

The latter generates a transmit command DREQ to the memory access control circuit DMAC which retrieves the digital values of a tone curve for a selected tone from the subsystem memory URAM.

In this manner, each of the microprocessors CPU and UCPU can read the subsystem memory URAM and/or store signals therein as if it were normally connected with the corresponding bus.

Since the operation of the subsystem memory URAM is faster than that of the microprocessors, it is permissible that the memory URAM be connected with the selected microprocessor only during a fraction of the interval of a cycle.

The bus switch, which alternately connects the subsystem memory with the main system bus and the subsystem bus, allows in effect a practically continuous exchange of data between the main system and the subsystem. This enables changes of input data identified by the main system to be transmitted to the subsystem and processed by the latter in practically real time.

A method of operating an electronic keyboard musical instrument in accordance with the invention is characterized in that the main system microprocessor and the subsystem microprocessor are operated at the same pulse frequency but effectively offset in phase by a portion of the cycle time. The offset may be so selected that during one half of the cycle time of the main system microprocessor the bus switch connects the subsystem memory with the main system bus and during the other half of the cycle time the subsystem memory is connected to the subsystem microprocessor.

With a tone module in accordance with the invention, it is advantageous to transfer all of the information which is requried for the generation of a tone from the main system computer via the bus switch into the subsystem memory after the actuation of a tone selecting key.

AS soon as a selected tone is to be generated, irrespective of whether it is initiated by an actuating key of the upper manual OM, the lower manual UM, the pedal PD or an accompanying automatic device, the main system writes parameters (for example, approximately 170 bytes) into the subsystem memory URAM by way of the bus switch BS and then transmits a "start" command into such memory.

Without latching the texture data, four (bi-linear filtering) or even eight (tri-linear filtering) unfiltered texels become necessary which would have to be provided by the memory subsystem per pixel.

The output of the parameter interpolator 18 is connected to a first input of a pixel pipeline 20 . The output of the pixel pipeline 20 is connected to a memory subsystem 24 via a packing unit 22 .

Among the new features in this new version of GNOME 2.26, KDE 4.2.2, the FreeBSD kernel virtual address space was increased by bringing it to 6 GB, the virtual memory subsystem now supports complete transparency in the use of superpages (1, 2) .

This compensation factor is stored in a subsystem of the therapy control system, namely, the subsystem for controlling the particle fluence, called SKT, prior to the irradiation of the i-th grid position, and subsequently, but still prior to the irradiation of the i-th grid position, loaded from the memory of the subsystem for controlling the particle fluence as the compensation value for the i-th grid position and multiplied in real-time by the nominal particle fluence defined for the i-th grid position in the irradiation plan, so as to calculate the compensated particle fluence (Ficomp) for the i-th grid position, with which the irradiation is then performed.

Preferably, the subsystem for controlling the particle fluence SKT controls the applied particle fluence for all grid positions, and the computing device stores the compensation value for the i-th grid position during the irradiation of the i-1-th grid position in the memory of the subsystem for controlling the particle fluence SKT, so that the compensation value for the i-th grid position may be loaded from the memory by the subsystem for controlling the particle fluence immediately prior to the irradiation of the i-th grid position.

If, at the planned start of the irradiation of the i-th grid position, the compensation value for the i-th grid position is not yet stored in the memory of the subsystem, it would be possible to vary the beam intensity or introduce a beam pause, at least until the compensation value for the i-th grid position is stored, so as to prevent the i-th grid position from being irradiated with an incorrect particle fluence.

Data from the memory subsystem 24 are supplied to the second input of the pixel pipeline 20 via a depacking unit 26 .

The single computer consists of one or several CPUs (C entral P rocessing U nits), i.e., of one or several central processors which, together with a Central Working Storage 16, process the data transfers between the Hosts 1, the Cassette Drives 2 and the Disk Memory Subsystem 3 .