Übersetzung für "Address instruction" in Deutsch

The decoder will take its base address from this instruction according to the following rule:

The 7070 was not designed to be instruction set compatible with the 650, as the latter had a second, jump address in every instruction to allow optimal use of the drum, something unnecessary and wasteful in a computer with random access core memory.

Both registers are inhibited after an address error, so that the address of the instruction which caused the memory protection alarm, as well as the address to which access was attempted, can be read out of the corresponding registers by a system program.

During program execution, the instruction is fetched from the location designated by the instruction address in IAR 32 and entered into instruction buffer register 10.

The instruction address is then passed to ALU 26 via ALU left input data path 44, incremented via ALU 26, and placed back in IAR 32 via data path 46 in order to address the next instruction in sequence.

The instruction address in IAR 32 is incremented via ALU 26 and placed back into IAR 32.

In order to increment or decrement an address, including the instruction address contained in the instruction address register, the present invention provides apparatus such that only the offset portion of the virtual address is passed through the data path associated with the CPU.

The acknowledgment pulse which is output by the control unit ST of the processor B and which indicates the end of the working off of an instruction in the processor, effects that the instruction address residing in the address buffer register AZR is written into the address register AR.

This instruction which is read at the next instruction address is always addressed by the instruction address residing in the current instruction indicator IZ.

In the parallel circuit arrangement, the interrupt requests pending at the inputs would simultaneously address the instruction indicator IZ over a logic circuit constructed of gates.

The address received by the instruction address register indicates the first instruction of an interrupt routine required for the execution or servicing of an interrupt request of a corresponding interrupt source.

As suggested previously, interrupt requests queued in the buffers BU of the processing elements PE are preprocessed, to form an initial routine address, by adding to a predetermined part of each request (i.e., the SLVL field) a base address, via an arithmetic and logic unit ALU in each processing element. Each routine address is transferred via a second buffer operated in accordance with the known FIFO algorithm into one or more instruction address registers IAR in the respective processing element for transmittal to a single or multi-processing system which performs the task routine.

A method as recited in claim 3, wherein a difference between the address of an instruction and the address of a preceding instruction is determined, said difference determining whether the later instruction is not a branch instruction (NBR), which is the case if this difference is 1 with instructions of equal length, or n if the instruction lengths differ by the value of n, wherein branch instruction (BR) is indicated if the difference does not equal 1 or n.

The address buffer register AZR always contains the address of instruction indicator IZ, i.e. the program level of the processor which the processor will work off as the next level.

Each of the instruction indicators always contains the instruction address by means of which the next instruction of the external program memory EPS is addressed as soon as the instruction indicator is addressed.

In this way a program is started which reads the address of the instruction which caused the memory protection alarm, and the address to which access was desired, from two registers of the memory protection logic.

In this case given instructions and/or data are set in the control register 14 in such a manner that in a subsequent address, instruction and/or data telegram the reception acknowledge signal for the data word DAT is in principle suppressed.

This function sequence may comprise the transmission of further, specifically configured address, instruction and/or data telegrams, but may also comprise accompanying measurements which are independent thereof.

To this end, in response to the appearance of an interrupt signal an address jump to a fixed predetermined address of the instruction memory is initiated, which address is situated within a very low address range, i.e. in the first segment.

The subroutine itself is not indicated, but it also commences with the instruction 6, like the previously described normal program jump, whereby the contents of the address "direct", i.e. in this case the value "0", are stored in the stack adjacent the address of the instruction counter 8 stored in response to the instruction 13.

This static instruction flow indicator indicates for each instruction address the instruction type, and whether the latter has an external entry associated thereto.

Before such real addresses of respective first instructions of interrupt routines can be transferred, via gates G80 to G8K(FIG. 2), into instruction address registers 25 to 27 (IAR 0 to IAR k), a test is made to determine if these instruction address registers do or do not contain previously loaded addresses.