Übersetzung für "Refresh cycle" in Deutsch

A refresh cycle may be performed if the charge level has dropped significantly.

Normally, therefore, the RAM memory unit is inhibited for the initiation of such normal memory cycles during the refresh cycle.

At least approximately, this next refresh cycle thereby corresponds to the immediate beginning of a new, first time interval.

Typically, a DCC command station will be repeat commands several times and later on, the command will be send in the general refresh cycle.

Per se, the self-discharge of the activated electrodes is most frequently low; however, it can be, even entirely, compensated in that the cyclic activation of the light switches, attainable by the intermediate switches, as a rule, represents a refresh cycle which eliminates the self-discharges of the electrodes which occurred since the last activation.

The refresh signal, which leaves the CPU and is placed on the semiconductor memory via the computer bus, immediately starts a refresh cycle in the semiconductor memory which consists of a complex sequence of different signals.

To date the procedure has been to assign the semiconductor memory the highest priority in the data bus, so that this semiconductor memory will perform its refresh cycle in any case, which naturally had the disadvantage that while the refresh signal was on the computer bus the external mass storage units were unable to transmit their signals over the computer bus, resulting in difficulties with data transmission or even data loss.

Only when all signals have the same logical state does the AND-gate conduct and transmit a refresh signal to the semiconductor memory, so that the semiconductor memory immediately generates a refresh cycle on the basis of this refresh signal.

The input 13 (K-input) thus remembers that during the refresh repeat cycle a request for transmission of a refresh signal 25 occurs.

Only when all three of the named signals are at logical 1 will the refresh signal RFR be placed on the computer bus on line 15 and transmitted to the semiconductor memory, which immediately generates a refresh cycle.

After output of a refresh signal RFR the flip-flop 14 is reset via line 21, so that a refresh signal can only be output once during the course of a refresh repeat cycle.

In other words, in a semiconductor memory configuration only the incorrectly set fuse latch circuits are reset, while the correctly set fuse latch circuit does not need to be reset during the refresh cycle.

A "refresh" cycle as just set forth is implemented within a count cycle of the global counter means GZ for all existing virtual connections, even when no message cell arrived for the respective virtual connection within this count cycle.

The present invention shall be set forth below in greater detail with reference to the drawings which relate to a specific example of a control unit for the execution of the refresh cycle of a RAM memory unit having, for example, 128 memory cells or, respectively, groups.

The refresh cycle 5 inserted in accordance with the present invention is therefore preferably triggered by a read cycle 1/2/3/4 of the RAM memory unit.

The second time interval s is variable and therefore potentially lasts, for example, between 0 and 5 ?s and the memory cycle 1/2/3/4 is intended to immediately trigger another refresh cycle 5 or 5 in the second time interval s.