Übersetzung für "Positive bias" in Deutsch

But the anode current may be increased through a positive grid bias voltage.

A reverse voltage is applied, such that the guard ring is provided with a positive bias voltage.

Moreover, the positive selection bias decreases with the income level of the sending country at a given income differential.

The Commission welcomes the positive overall findings of the independent evaluation of the EYD201516, while acknowledging that some conclusions need to be considered in the light of the data gathering constraints encountered, and the fact that the evaluation draws extensively on a survey of stakeholders who themselves implemented campaign activities, which implies a potential risk of positive bias.

Thereby, the feedback resistor 97 displaces the positive bias voltage at the non-inverting input of the operational amplifier 94 in the negative direction and thereby assists the initiating cause.

If this concerns MIS structures of the enhancement type, then a positive bias voltage is to be supplied to G, which voltage is eliminated for a short period of time by means of a negative pulse P1, or it is overcompensated.

From the models and supporting organizations reviewed, even if their achievements are more than somewhat overstated due to the inherent positive bias of the available sources, it appears certain that intentional communities do indeed offer an alternative to industrial un- and underemployment to quite a number of per sons.

The electrode 313 lies at a positive bias voltage (+), whereas the electrode 333 lies at earth.

The noise generator 61 can be implemented, for example, with a zener diode whose cathode is connected through a resistor to a positive DC bias and whose anode is grounded, as is known from DE-C2 28 20 426.

The noise generator 61, for example, can also be implemented with two zener diodes whose respective cathodes are connected through a resistor to a positive DC bias and whose anodes are grounded.

Given a positive bias of the semiconductor substrate, the pn-junction between the third and fourth semiconductor layers can be biased to such an extent in conducting direction that a current path that is to be attributed to a parasitic thyristor effect within this four-layer structure arises between the said transistor terminals.

The current path then continues to be present after a dismantlying of the positive substrate bias and can thermally overload the integrated circuit.

Given a positive bias of the semiconductor substrate, the pn-junction between the third and fourth semiconductor layers can be biased to such an extent in conducting direction that a current path arises between the said transistor terminals, this current path to be attributed to a parasitic thyristor effect within this four-layer structure.

The current path also continues to be present after the dismantling of the positive substrate bias and can thermally overload the integrated circuit.

This is caused by the fact that the complementary MOS-transistors in the switch are correctly brought into the conducting condition by a positive bias, that however the change into their blocked condition is performed only by dropping this bias.

A second terminal of the second p-channel field effect transistor P2 is connected to a positive bias voltage VDD and a second terminal of the first p-channel field effect transistor P1 is connected to the rectifier unit GR'.

During operation of the integrated circuit as well, however, larger currents which are sinked from the semiconductor substrate via the substrate bias voltage generator to a terminal of the latter lying at ground potential can lead to a positive bias voltage of the semiconductor substrate due to the voltage drop at the internal resistance of the substrate bias voltage generator.

Positive bias voltages, however, represent a high safety risk for the integrated circuit since a "latch-up" effect can be triggered, this usually meaning the failure of the integrated circuit.

Given a positive bias voltage of the semiconductor substrate, the pn junction between the third and fourth semiconductor layers can be biased to such a degree in the conducting direction that a current path arises between the mentioned transistor terminal, this being attributable to a parasitic thyristor effect within the four-layer structure.

The current path then also remains after the positive substrate bias voltage disappears and can thermally overload the integrated circuit.

When the semiconductor substrate 1 lies at a positive bias voltage, then the gate 22 is also correspondingly positively biased, this leading to the fact that when the low threshold voltage is exceeded that the switching transistor 20-23 becomes conductive.

For example, this clamping effect occurs when, by switching on the supply voltage VDD, the semiconductor substrate 1 is boosted to a positive bias voltage by the capacitive voltage division between the terminals 14 and 8 as long as the generator 16 does not yet supply the full negative bias voltage.

When high currents derive during operation, these flowing off via the semiconductor substrate 1 and the elements 18, 17 and 16 to the terminal 16a which lies at ground potential VSS, then such a voltage drop can occur at the internal resistor W of the generator 16 that the output 17 and, therefore, the semiconductor substrate 1 are at least temporarily placed at the positive bias voltage.

Likewise, there is prevented as a result that the conductive coating 14 represents a low resistant bridge of the pn junction between the base 2 and the emitter 4 and an adequate positive bias voltage is not established at the emitter 4.