Übersetzung für "Steigende flanke" in Englisch

A rising flank 61 is shown in the first voltage profile 51 .

The booster 25 is used to generate such a rising edge nevertheless.

The T flip-flop 50 reacts to the rising edge of the carry signal.

Different references can thus be provided for the rising and falling edges.

The interrupt signal is generated, for example, as a rising edge of a digital signal.

The leading edge, the peak or the trailing edge of the pressure increase may be used.

The second rising edge SF6 is associated with bit 6 of the serial value SD.

The read operation starts when, by way of example, a rising edge of the precharge signal is detected.

To this value the counter will be set if a rising edge is detected at the S-input.

This rising flank 61 symbolizes the closing of the second switch 12 for the wire-break test.

Instead of a synchronization to the falling edge, it may also be synchronized to the rising edge.

The rising edge 39 ? is also shaped accordingly after the time window 35 has elapsed.

Each falling and each rising edge of the symmetric sawtooth-shaped control signal corresponds to a passing through of the absorption line.

The gradient pulse shape has a plateau with constant amplitude, a rising edge and a falling edge.

Thus, for example, a rising or falling flank of the corresponding measurement signal is used as start- or stop-trigger.

The corresponding rising flank 46, however, does not yet result in a switching back on of the actuator.

This can be, for example, a falling or rising edge of a digital synchronization signal.

This is represented in FIG. 5 at the point in time t 4 by a rising edge of the confirmation signal ACC.

Each rising and trailing signal edge is however detected on the V-IN line 8 .

The rising and falling edges of the clock (clk) are used for the signal sampling.

In a step S 2, it is checked whether or not the measuring signal MS has a rising edge.

In a step S 2 a, it is checked whether or not the measurement signal MS has a rising edge.

If there is a rising edge at the input ZR the count will be decreased by 1.

If there is a rising edge at the CU the count will be increased by 1.

In order to obtain results which can be reproduced even better and which are more exact, the invention provides that the time/amplitude converter circuit is stopped with a predetermined delay by the rising edge of the appropriate oscillator pulse in the case of each time interval measurement and each calibrating measurement, and that the time/amplitude converter circuit is started after each of these measurements by a start signal produced within the circuit and is again stopped by a stop signal, which is produced at the same time as this start signal and is also subject to the predetermined delay, and that the correction value thus obtained is subtracted from the time value obtained beforehand.

If the inverted output signal of the monostable multivibrator MF2 being triggered at the trailing edge is at the high level, then a control pulse of the regulating circuit RS is switched by the AND gate ANDa to the signal input of the monostable multivibrator MF1 being triggered at the leading edge.

If a leading or trailing edge of the data signal is located at the input of the signal-processing circuit at the instant of weighting by its system clock pulse, the result is weighting uncertainty, which leads to jittering having the width of one clock period.

If a leading edge of the data signal B is located within a predefined region (drawn in broken lines in FIG. 4 as an example), then a short pulse is generated at the output of the AND gate 8.