Translation of "Während des testens" in English

During testing of the circuit, the bonding pad is exposed to mechanical stress by test needles.

Hoses are often used as a temporary solution or in the test phase of new production lines.

Provides an interpreter to avoid compilation when testing.

During testing of the circuit component SK 1, the test control signal has the value “0”.

The width of the reading windows of the storage transistor of cells 20 to 43 can be reduced and tested during the functional testing, such as through a programming time control shown in detail in U.S. Pat. No. 4,279,024, incorporated hereinto by reference, so that during the testing, the reading window is not only made narrower but the reprogramming of the storage cells is also controlled in such a manner that the reading window reliably encloses the reading voltage.

The memory device according to claim 12, wherein said comparison units are selectively activatable and deactivatable, during the testing of the memory device, independently of whether said comparison units are activated or deactivated in normal operation of the memory device.

During the testing of the memory device, the comparison units can be placed into a state which differs from the state of the comparison units during the normal operation of the memory device.

Although only a relatively small part of the integrated circuit is tested during such tests, such tests are frequently relatively complex, particularly on account of the very high currents that can flow through the integrated circuit during testing, and on account of the associated extreme evolution of heat.

The fact that, while it is being tested, the tested circuit component does not output data to the bus, and/or that it outputs data other than data which is output in the normal case, does not affect the test result.

If the circuit component SK 1 were to automatically deactivate its output drivers (put them into the high-impedance state) during testing, this could lead to problems.

There are innumerable other options for this: by way of example, a NAND gate may be used instead of the AND gate AND. As another example, a multiplexer can be used to selectively connect, to the output driver T, the data DOUT which need to be output during normal operation or data which need to be output during testing.

The electrical circuit can alternatively be designed such that, while it is being tested, the circuit component which is to be tested outputs no data to the bus.

The result of this is that the signal used to control the output drivers T continuously has the value “0” while the circuit component SK 1 is being tested, as a result of which the output drivers T are deactivated and cannot output data to the bus “BUS”.

The fact that no data are output to the bus “BUS” while the circuit component SK 1 is being tested has the positive effect that the output drivers T have no or only a negligibly low power consumption and consequently do not heat up at all, or heat up only to a very small extent.

Like the circuit component SK 1 shown in FIG. 1 and by contrast with the circuit component SK 1 shown in FIG. 2, the circuit component SK 1 shown in FIG. 3 outputs data to the bus “BUS” as required (particularly when the circuit component SK 1 is determined by the bus control device BUSCONTROL as bus master) while the circuit component SK 1 is being tested.

Whether leakage currents occur and, under certain circumstances, whether the leakage currents are within or outside a tolerable range may be recognized by connecting the supply line to a test voltage source and inserting a high-ohmic resistor, interrupting the voltage supply during the testing operation by means of the relay, and measuring the potential which prevails on the supply line during this test period.

This means that the value “0” is continuously output to the bus while the circuit component SK 1 is being tested.

The fact that, while it is being tested, the circuit component SK 1 outputs data which never change or change only infrequently to the bus “BUS” has the positive effect that the bus lines need never be reloaded or need be reloaded only infrequently.

The fact that the data DOUT which actually need to be output to the bus “BUS” are not output to the bus while the circuit component SK 1 is being tested, but instead other data are output to the bus, has no negative effect on the test result.

The fact that the output drivers T are deactivated while the circuit component SK 1 is being tested has the positive effect that they have no or only a negligibly low power consumption and consequently do not heat up at all or heat up only to a very small extent.

In other words, during the testing of the memory device, the comparison units can be placed into a state which differs from the state which the comparison units are in during the normal operation of the memory device.

During the testing of the memory device, the comparison units can be placed into a state which differs from the state which the comparison units are in during the normal operation of the memory device.

Naturally, during testing of the memory device, any other controls or settings of the comparison units or other components of the memory device can also be changed additionally or alternatively as described or differently.

Further analysis of collected data allows you to detect and solve issues during Modbus testing and debugging.

With the experiment software ControlDesk, you can monitor all important signals and variables during the test process to get a clear overview or manipulate its values during run time.

All data collected during testing is used to customize a Series i system to your specifications.

By testing individual, we must not forget that the severity of symptoms depends on the amount of residual intestinal lactase, the amount of lactose consumed and the conditions of ingestion (for example, if lactose is ingested on an empty stomach, with or without other foods).