Übersetzung für "Wafer level packaging" in Deutsch

In US 2005/0184304, a wafer level packaging method is presented for the encapsulation of micromechanical surface fabricated micromirror arrays.

Integrated electronic components are produced nowadays by employing, inter alia, various wafer level packaging methods.

Wafer level packaging in LED manufacturing is still very much in the developing stage, yet this technology promises tremendous potential.

Main areas of application are primarily fastidious Belackungsprozesse in the ranges the wafer level Packaging applications as well as the 3D-Integration.

In the area of the wafer level Packaging and the 3-D-Systemintegration the researchers developed themselves also internationally an outstanding position.

Special application fields are exposure processes with thick photo resists for advanced packaging, wafer level packaging and 3D integration as well as the production of MEMS.

During the preparation of the chips on the wafers, after application of the transparent covering they can be packed using various wafer-level packaging processes.

Housings for encapsulating MEMS/MOEMS and methods for producing such housings particularly at the wafer level, so-called wafer level packaging methods, are known from the semiconductor industry.

In WO 2004/1068665, a wafer level packaging method is described for MOEMS that provides for a glass cap substrate.

Packages for encapsulating microsystems, customarily MEMS/MOEMS, and methods for fabricating such packages, in particular at the wafer level, so-called wafer level packaging processes, are known from the semiconductor industry.

The inventive cover is preferably used for encapsulating microsystems at the wafer level, in particular by means of wafer-level packaging methods.

In WO 2004/1068665, a wafer level packaging method for MOEMS is described that provides a cover made of glass.

The process is particularly suitable for packaging components which still form part of a wafer (wafer level packaging), in which case the substrate comprises a wafer having the substrates of the components, which can be separated from the wafer after they have been packaged.

Furthermore, the method according to the invention also integrates the wafer level packaging through the application of the patterned support at least partially with the provision of further functional structures or elements, such as, for example, optical lenses for optoelectric components.

The so-called Wafer-Level-Packaging (WLP) enables the encapsulation of open sensors at the wafer level.

The fabrication of vertically conductive connections through a chip with an integrated circuit (wafer-level packaging) is described for the use in multi-chip stacks.

In combination with new biocompatible forms of glass, entirely new uses of wafer-level chip-scale packaging (WL-CSP) are now possible.

The possibility of additional wiring area around the chip proper means that the wafer-level packaging technology also lends itself to new, space-sensitive applications.

Alignment of the structuring on the wafer back side with the structures on the front is required in processes involving applications such as MEMS, wafer-level packaging and 3D integration, where used for example to create vertical through silicon vias (TSVs) on interposers.