Übersetzung für "Untersten zeile" in Englisch

Turn to page 40 and begin at the bottom line, will you?

Additionally, in the lowest line of FIG.

The next upcoming turn-off is shown in the bottom line.

The voltage present at the port P 4 can be extracted from the bottom trace of FIG.

Available function key combinations (FX) are shown in the bottom line of the YaST screen.

The previously entered letters are displayed in the bottom line of the screen.

The lastest message appears at the lowest line.

Try not to break the pattern on the bottom line bending.

If the cursor is already located in the bottommost line, nothing happens.

The bottom line displays the city where the street is being searched.

Available F key shortcuts are shown in the bottom line of the YaST screen.

Define what should be specified in the bottom line of each page here.

Where the number of all services covered by the package of services is not limited, payment service providers shall delete the statement at the bottom of the row ‘Services beyond these quantities will be charged separately’.

The clock signal ?E will then transfer bits 10, 12, 14, 16 into alternate charge storage sites of the uppermost row of parallel section P, while simultaneously bits 9, 11, 13, 15 are transferred into alternate charge storage sites in the lowermost row of parallel section P, in a manner similar to that shown by the transition occurring from FIG. 3 to FIG. 4 and described above.

The next pulse appearing at the output Cout of the Johnson counter 120 arrives at the clock input of the flip-flop 122 whose D input is always at logical 1 so that now the flip-flop is set at its Q output to logical 1, as is illustrated in the bottom line of FIG.

FIG. 4 illustrates the phase modulator selection signals for sequential (time-division multiplex) readout of the rotational rate signals for the three spatial axes (i.e. for the channels x, y and z.) Once again, the selection pulses of the light source LQ (superluminescent diode SLD) are shown at the lowermost line.

For this reason, the time/amplitude converter circuit 88 is started simultaneously with the rising edges of each of the output pulses of the gate 84, each corresponding to a transmitter signal. The output signal of the time/amplitude converter circuit 88 increases, as shown in the bottom line of FIG. 7, at first non-linearily and then, at the latest after the elapse of the period t, exactly proportional to the time.

FIG. 4 illustrates the phase modulator selection signals for sequential (time-division multiplex) readout of the rotational rate signals for the three spatial axes (i.e. for the channels x, y and z.) Once again, the selection pulses of the light source LQ (superluminescent diode SLD) are shown at the lowermost line.

If the differential signal of the two photodiode output signals is formed by electronic means, that produces the receiver output signal which is shown in the bottom line in FIG.

Illustrated in the lowermost line of FIG. 15 is the voltage course at that end of the cable portion, which lies opposite the input end and possesses a spacing of about 1000 meters from the input end.

The clock signal ?E will then transfer bits 10, 12, 14, 16 into alternate charge storage sites of the uppermost row of parallel section P, while simultaneously bits 9, 11, 13, 15 are transferred into alternate charge storage sites in the lowermost row of parallel section P, in a manner similar to that shown by the transition occurring from FIG. 3 to FIG. 4 and described above.

The next pulse appearing at the output Cout of the Johnson counter 120 arrives at the clock input of the flip-flop 122 whose D input is always at logical 1 so that now the flip-flop is set at its Q output to logical 1, as is illustrated in the bottom line of FIG. 10.

In the lower line is shown the course of the measured signal y(t) given by the system to be investigated.

Bugfix: Bricks in the row at the bottom could still be rotated although parts of them disappeared in the ground.

Around them, pour the foundation about 30 cm deep. Drill holes and set him on the bottom row of anchor logs.

Page dismissed the question as having a “short-term focus” and said that developing and pushing out Android was about much more than the bottom line.

At the bottom line you can rate a level with values from 0 (bad) to 10 (top).

Finally, the voltage which is applied to the detection input via the summation point 20 of the voltage divider 26 is illustrated in the lowermost row of FIG. 3, said voltage being monitored for control purposes and being used to check whether the power switch 4 is on.