Übersetzung für "Instruction counter" in Deutsch

The instruction counter BZ serves as an input register of the instruction memory BSP.

Otherwise, the instruction counter BZ is merely incremented (signals ST6).

When the branch condition is not fulfilled, the instruction counter BZ is incremented in a standard way.

As is well known in the art, the instruction counter of a central unit, such as a microprocessor, only has a limited address stock.

In this manner, the instruction cycle counter is stopped on cycle time T4 for two cycle times.

The alternative embodiment of an instruction cycle counter also consists of flipflops 54 generating cycle times Ti.

In the performance of the program, the operational portions of the command words of the program memory are processed according to the steps of the instruction counter, corresponding exactly to the serial-logic interconnection of the embodiments of FIGS. 12 and 13 which operate purely in hardware.

During the phase 2, the instruction counter BZ is incremented and the next instruction word is written into the instruction register BZ during phase 3.

Given a branch instruction, the branch condition is checked in phase 3 and the absolute address is taken from the instruction word given an appropriate result and is loaded into the instruction counter BZ.

When a branch instruction is involved and when the FLAG conditions (signals ST5 from the ALU) agree, then the instruction counter BZ is loaded with the new address (signals ST3).

An instruction counter BZ in which the address under which the next instruction word to be processed is stored in the memory BSP is formed is also required for the execution.

In this task switching, which is triggered with a microprocessor branch instruction, the microprocessor register contents, for example segment register, instruction counter, but not the interrupt descriptor table register IDTR and the global descriptor table register GDTR belonging to the currently-running task of the real-time operating system are automatically entered into the status segment RT-TSS of the real-time operating system by the microprocessor and are replaced by the corresponding values from the status segment TS-TSS belonging to the subscriber operating system.

The number of instructions is counted by an instruction counter 23, which is connected to a switch 24.

With such an instruction cycle counter 22a the operation decoder 15 can be of a less complicated structure since e.g. for the two microinstructions of the above type it merely has to generate always the same control signals for the data flow.

In the performance of the program, the operational portions of the command words of the program memory are processed according to the steps of the instruction counter, corresponding exactly to the serial-logic interconnection of the embodiments of FIGS.

The data path controller is composed of the instruction register BR, of the instruction counter BZ, of the address decoder ADRDEC and of the instruction decoder BEFDEC.

Data Sheet MC 68 F 333 TS/D, Motorola 1992, already discloses a microcomputer which has, apart from the central processing unit, a programmable, non-volatile memory (flash EEPROM), input/output components, a monitoring circuit (watchdog timer), and also a volatile memory (code RAM), into which there can be written program data which can be accessed by the instruction counter of the central processing unit.

The subroutine itself is not indicated, but it also commences with the instruction 6, like the previously described normal program jump, whereby the contents of the address "direct", i.e. in this case the value "0", are stored in the stack adjacent the address of the instruction counter 8 stored in response to the instruction 13.

Finally, by way of the instruction 5 the contents of the instruction counter 8 are stored in the stack, after which the program counter 8 is set to the address at which the sub-routine commences in the relevant segment, and at the same time a load signal for loading the contents of the register 4 into the register 2 is generated again via the OR-gate 22, the AND-gate 24 and the block 36.

The present invention relates to a method and to a circuit arrangement for expanding the addressing capacity of a central unit, in particular of a microprocessor, beyond the base address capacity defined by the address stock of an instruction counter.

SUMMARY OF THE INVENTION Consequently, the object of the present invention is to provide, by way of a method and circuit arrangement of the type generally mentioned above, that the addressing capacity of a central unit, in particular of a microprocessor, can be expanded in a relatively simple manner beyond the address capacity defined by the address stock of the instruction counter, without the necessity of two or more central units.