Translation of "Timing pattern" in German

The user data packets can be transmitted at any chosen times taking into consideration the timing pattern.

However, it can also be adapted by measuring the overall time period in a certain timing pattern.

Since further the control signals to be synchronized into the timing pattern of the outputting system are always correlated with a possible forwarding pulse, that point in time beginning when a memory section is available for the acceptance of a new data word is always fixed so that it is always only one data word which is transferred into the buffer memory in the steady state condition when an intermediately stored data word is previously forwarded.

The OR element 051 thereby assures that, given even greater in-synchronization times, the forwarding of the intermediately stored data words can continuously occur in the timing pattern of the accepting clock system f2 without gaps arising in the data flow because the entire in-synchronization time in the last asynchronous register R1 of the series must be marked or identified.

Connected in series with the synchronizing flip-flop SYN-FF11 is a further synchronizing flip-flop SYN-FF12 which is likewise clocked with the trailing edge of the clock pulses of the forwarding timing pattern f2 and which indicates whether a data word is proceeding for forwarding or not.

Accordingly, tRAST2 must signify a waiting time beginning with occupation up to the appearance of a clock pulse in the clock system f2 and tSYN2 must signify a delay time for bridging the metastable statuses until the intermediately stored data word can be finally forwarded with a signal w1 initiated upon the subsequent clock pulse of the forwarding timing pattern f2.

In this case, the write clock ST is formed by the supplied strobe signal STR, and the read clock LT is formed by the clock pulses of the timing pattern f2 of the transmission system.

The setting outputs of all control logic elements K-FF1 through K-FF3 and of the input flip-flop FA-FF0 are combined over an OR element 051 whose output signal dv' corresponds to the control signal dv indicating the presence of intermediately stored data already acquired. The control signal dv is synchronized into the timing pattern f2 of the accepting system SYST2 by the synchronization circuit SYN2, and leads to the signal w1 as the transfer clock UT for the synchronous register R0.

As tSYN1 =t1, it is a further pulse of the timing pattern f1 which then supplies an output pulse f1' which simultaneously resets the trap flip-flop FA-FF over the AND element U2.

The resetting of the input logic elements EIN . . ., which occurs one clock period t2 earlier, assures that the following control signal dv is incorporated in the timing pattern f2 at the right time in order to enable a continuous data out-flow.

For this purpose, the setting output signals of the occupancy logic elements BEL0 through BEL3 are inverted and are combined over an OR element 02 to form the signal st' which, as an already acquired control signal st, influences the synchronizing flip-flop SYN-FF which is clocked with the clocks of the other timing pattern f1. Over a following AND element U5 according to FIG. 6, this signal supplies the call signal f1' synchronized into the system SYST1.

I.e., as soon as the buffer memory PUF is filled and the control signal st' becomes zero, the synchronizing flip-flop SYN-FF is instantaneously reset over the inverted reset input R so that two clock pulses of the timing pattern f1 are required and a request pulse f1' again appears at the output of the synchronization circuit SYN1, as shall be illustrated later on the basis of the corresponding pulse diagram.

As long as all occupancy logic elements BEL0 through BEL3 are not set, there is still space in the buffer for the acceptance of a data word and the control signal st' indicates the free status with the consequence that each clock pulse in the timing pattern f1 becomes a request pulse f1' after the synchronizing flip-flop SYN-FF has been set.

When all registers are occupied, however, even if only briefly, for example with the transfer of the data word E, then the synchronizing flip-flop SYN-FF is instantaneously reset and the next clock pulse in the timing pattern f1 of the outputting system does not lead to a request pulse, for example at points in time X and Y, since the synchronizing flip-flop SYN-FF must still be reset.

In other words, the in-flow ensues given a higher clock frequency of the outputting system controlled with an intermittent clock in the timing pattern of the outputting system given automatic matching to the maximum data rate conditioned by the accepting system without a separate request/acknowledgement system being required for that purpose.

This results in the fact that, in contrast to the sample embodiment according to FIG. 1, data words DAT are continuously input into the buffer memory PUF with successive clock pulses of the timing pattern f1 until the signal frei is omitted and that thus the buffer memory is more rapidly filled with a plurality of data words securing a continuous data flow at the output of the buffer memory.