Translation of "Serial section" in German

See the Serial Communications section in the FreeBSD Handbook.

By clock signals applied to the control logic circuitry, the alternate odd bits A1, A3, A5, A7 are transmitted from the I/O INTERFACE L2 along lines 1, 2 to the regenerator R1 and then by line 4 to the serial input section SI1 of LOOP 1.

In a similar manner, the alternate even bits X2, X4, X6, X8 of the data bit stream are transmitted to the serial input section SI1 of LOOP 1 and are interlaced in said serial input section with the previously transmitted alternate odd bits A1, A3, A5, A7 of the first record, to provide in the serial input secton SI1 of the first loop the bit sequence shown in FIG.

The alternate even bits A2, A4, A6, A8 of the first record of the serial data bit stream are transmitted by timed clock signals from I/O INTERFACE L2 through lines 1, 3, regenerator R2 and line 5 to the serial input section SI2 of LOOP 2.

In a similar manner the alternate odd bits X1, X3, X5, X7 of the second record are transmitted to said serial input section SI2 of LOOP 2 and are interlaced with the even bits A2, A4, A6, A8 previously transmitted so as to provide in serial SI2 the bit sequence shown in FIG.

Upon subsequent transfer of the row of charge packets from the serial input section to the first row of the parallel section, the bypassed set of sites of the serial input section will be devoid of any charge packets and hence there will be no transfer of a charge packet into the first site of the defective column, thereby effectively bypassing the latter.

For example, in a four-phase arrangement, each serial section must have four extra sites for each redundant column in the parallel section.

When each row of charge packets reaches the last row of storage sites in the parallel section, the row is then transferred in parallel to the serial output section from where the charge packets are shifted serially from the output port designated "Out."

This first charge packet will then flow through column C9 as each successive row is transmitted toward the serial output section and then will be transferred to the extra redundant set O9 of the serial output section during the parallel transfer of the row of charge packets to the latter.

In a similar manner, bits 10, 12, 14, 16 are shifted serially through the first serial section S1, as shown in FIG.

The serial stream of hole charge packets is then output from the serial shift register section at buried charge output port 12, 13, 14.

The running-up phase is accelerated by deriving the supply voltage of the regulating circuit from the rectified line voltage via a serial timing section having as short a time constant as possible during the switching-on phase and only later from the sensing circuit.

In each of these figures the serial input register section is indicated at S and the parallel section is indicated at P. Only the first two rows of the parallel section P are shown.

For simplicity and clarity in illustration, the serial input section S is shown as having only eight charge packet storage sites, and the parallel section is shown as having only eight columns each associated with a respective one of the serial section sites.

During this process, successive rows of charge packets are similarly being transferred through the parallel section from the serial input section to the serial output section.

However, SSH access is possibly deactivated and has to be enabled via the CLI or the GOS-Admin-Menu through the serial console (see section SSH Access).

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At the left end of the serial input section as viewed in the drawing, the arrow designated "In" refers to the input port through which a serial stream of data bits is transmitted to the serial input section.

The parallel section comprises eight channels or columns extending vertically in the drawing and each designated by respective one of the references C1' to C8' forming in effect a matrix of rows and columns of storage sites with each column constituting a path for charge carrier packets to flow in sequence from a respective one of the storage sites of the serial input section to a respective one of the storage sites of the serial output section.