Translation of "Interrupt level" in German

A characterization for such an old processing element (old PE) is an OPE-register set to 1, an RPE-register reset to 0, and a D-register loaded with the corresponding interrupt level.

In an unmasked operation interrupt requests stored in memory 5 are associatively searched for a match to the interrupt level LV currently stored in register 8.

Masking circuit 6 substantially consists of a decoder DEC for transforming the interrupt level code LV into another code represented in the lower part of FIG.

At the beginning of initialization, there exist in the interrupt control only so-called neutral processing elements (neutral PE), i.e. such elements which have not yet been allocated to an interrupt level LV.

Furthermore, if a reserve processing element RPEi assigned to the same interrupt level i has been activated the interrupt requests in the primary processing element PEi must first be processed before routines can be started for the interrupt requests in the reserve processing element.

An interrupt targets a hart of a certain level, interrupt enable bits enable or disable application specific interrupt sources.

Each slave may provide an empty frame with data and transmit those data and/or at least a request in the form of what is commonly referred to as a “soft interrupt” and thus a software interrupt, for example of a second-level interrupt handler (SLIH), that is, a control program for interrupting a second layer in accordance with the OSI layer model, to the master as a response to the polling.

Each slave is able to use an empty frame and transmit its data and/or at least a request in the form of what is referred to as a “soft interrupt” and thus a software interrupt, for example of a second level interrupt handler (SLIH), that is, a control program for an interruption of a second layer in accordance with the OSI layer model, to the master as a response to the polling.

Now you have set by the publisher and the ad interrupt, channel, whose level is not discussed.

This kind of interrupt, as well as the IO-APIC-level interrupt, are only seen on systems with processors from the 586 family and higher.

This allows filling of the vaporizer to be interrupted if the level detector fails.

Treatment should be interrupted when creatinine level is 50% above the upper limit of normal.

In the last operating step VI of standard operation an instruction in the interruption handling program is located via passage of the initial instruction address of an interrupt routine to the associated processor, and executed while transfers from processing elements with lower interrupt levels are blocked.

Such processing elements whose D-registers are now loaded with interrupt levels, and in which the RPE-register and the OPE-register are still set to 0, are called standard processing elements (standard PE).

If the fan is switched off and the fresh air feed interrupted, the fluid level can rise in the aeration shaft 10.

The flexibility/adaptability of the present interrupt device derives from the co-operation of memory 5, controls 9, and masking circuit (SV) 6, the latter circuit controlling the assignments of levels to the processing elements PEi, if required, and the manipulation of interrupt levels through masks, if necessary.

As pointed out at the beginning of the specification, the initialization phase comprises the setting of the D registers with the information of interrupt levels LV which are to be allocated to respective processing elements.

Blood cell count should be monitored on a regular basis and treatment should be interrupted if level of Hb decreases 25% and one of neutrophils does 50% from the initial level.