Translation of "Bit frequency" in German

In this manner the clock frequency and bit frequency in the two interfaces are equal.

Thus, this signal has a recurrent frequency which amounts to twice the nominal bit cell frequency.

Bit rate, frequency and Mono/Stereo settings can be easily adjusted.

The product of the bit-rate frequency and the transmission length is therefore limited.

Additionally we can set parameters of the format, like bit rate, frequency, mode.

Clock signal CLOCK, which predetermines the bit frequency (for example 12 MHz for the present 4:3 format).

Whether quality or file size of your preference, the bit rate, frequency and other parameters set offers.

The improvement of claim 1 wherein the oscillator means further supply a second control clock pulse train having a nominal frequency which is higher than twice the bit cell frequency and where the clock extraction means comprise a clock pulse input for receiving said second control clock pulse train and further function to form therefrom, in connection with the received signal, elements of a read clock pulse train which are delayed with respect to the received signal.

It is an object of the invention to provide a device of the kind set forth which requires only a short period of time for adjustment during the synchronisation operation, but which follows exclusively long-period variations of the bit cell frequency during the subsequent reading of the data information.

Therefore said clock extraction device preferably comprises a clock input for receiving from said oscillator a second control clock pulse train (CL) having a nominal frequency which is higher than twice the bit cell frequency in order to form therefrom, in conjunction with a signal transition of the medium signal, an element of the read clock pulse train which is delayed with respect to this signal transition.

If the frequency of the former control clock pulse train (CP) deviates from twice the bit cell frequency, the read clock pulses thus developed are not situated each time exactly one half bit cell from each other. However, as the synchronization operation progresses, this inaccuracy diminishes when the frequency of the control clock pulse train becomes better synchronized with the bit cell frequency.

Thus, on the output line a (second) control clock pulse train CL is generated which has a frequency amounting to a multiple of the bit cell frequency (the nominal value of the latter is 500 kHz as has already been stated).

Thus, during the synchronization operation a phase comparison is performed twice during each bit cell, the intervals of the two pulses of the signals DC, DS and CP shown in FIG. 3 not being dependent on the bit cell frequency determined by the instantaneous speed of the record carrier, i.e. on the intervals of the signals supplied by the amplifier 31, before successful synchronization, but only on the instantaneous frequency of the voltage-controlled oscillator 15; however, the phase shift and hence the correction signal of the phase comparator remains substantially the same.

The PCM signals having a high bit sequence are scrambled in a plurality of parallel channels having a lower bit repetition frequency and the signals which arise are combined by multiplexing.

The code converter contains a phase control loop having a receive-side generator G which oscillates at the bit clock frequency of the outgoing signals. The second word clock is generated from this bit clock by a second frequency divider TT2 and is output to the intermediate memory ZS as well as to a phase discriminator PD.

The digital signals are scrambled in a plurality of parallel channels with a correspondingly lower bit repetition frequency and the signals which are formed are combined by multiplexers.

It is an object of the present invention to provide a self-synchronizing scrambler which is suitable to transmit digital signals of a high bit repetition frequency and which at a comparatively cheaper outlay dispenses with a demultiplexer and which has a period that can be selected to be independent of the operating speed and where it is also possible to suppress undesired short periods within a viable outlay.

An input 2 receives a clock frequency T1 which may deviate slightly from the bit sequence frequency of a digital signal D1 at the input 1 and may have an arbitrary phase position with respect to it.

In this, specific multiplex signals, also called multiplex elements, are precisely specified with respect to bit sequence frequency and structure of the pulse frame, e.g., so-called `virtual containers`.

If a digital signal of the plesiochronous hierarchy, e.g., a multiplex signal with 139,264 Kbit/s of the fourth stage of the European hierarchy or, for example, a digital television signal coded with the same bit sequence frequency is to be transmitted in a transmission network with the synchronous hierarchy, then it is provided that this signal is inserted into the multiplex signal corresponding to it, the so-called 'virtual container`.

It consists of the addition of additional words, called `bytes`, for adaptation to the bit sequence frequency or transmission capacity of the particular multiplex signal and of the bitwise stuffing for frequency matching.

With bandpass signals whose signal of which the content is derived from a sequence of binary values based on a bit clock frequency fb, it is advantageous for the sampling frequency fa to be chosen to be equal to the bit clock frequency fb.