Übersetzung für "Row decoder" in Deutsch

The row decoder then activates the corresponding word line.

Moreover, a control signal A is fed to the row decoder RDEC.

The write/read signal RWQ must be supplied to the row decoder ZD in the SRAM architecture.

At least the row address decoder 4 must have memory characteristics because of the address input operations which are consecutive in time for row and column.

The setting information is provided by a processor P, not shown, to a column decoder Dx and a row decoder Dy.

The invention preferably involves an integrated semiconductor memory matrix which is provided with a row address decoder as well as with a column address decoder.

In cases where a column or a block decoder is provided for distinguishing several storage bytes along one row then, these decoders may also be provided with even/odd selecting capability analogous with the aforedescribed design of the row decoder.

Accordingly, in an electrically programmable memory matrix according to the invention, upon application of a logic low or "L" TEST signal to E2 and the following programming operation, there is effected a simultaneous programming of several memory rows with the same bit pattern along each row, when the respective outputs of the row decoder Dz conduct the programming potential Vp.

Address lines leading from the row decoder 61 to the memory 7 are also connected through a further or second selection unit 13 to the address control unit 4.

This information is used to make the sources 6 of all those columns which are associated with lower column lines completely active and independent of the condition of the row decoder 2, while the source of those columns which have higher significance cannot be activated.

The information from the row decoder 2 and the column decoder 3 is therefore interlinked with the additional information at the matrix point 5 to form a control signal for the individual source 6.

A further saving of area with a simultaneous satisfactory suppression of the overvoltage peaks, is achieved by saving input lines by tying together matrix elements 5 according to the weighting and the row decoder.

During the active reading, writing and erasing modes of operation, all outputs of the row decoder Dz, with the exception of one selected output, are connected to a potential Vo corresponding to a "low level."

The gates of the w.b=m selection FET's of each row are connected via a common row selection line to each time one of n outputs of a row decoder.

As a rule, it is completely sufficient to design either the row decoder Dz or the block decoder Db in accordance with the invention, and to divide it in two parts with associated circuitry in order thus to block subsequent programming following an initial programming operation which might take place, for example, for balancing a television receiver.

The invention relates to a memory matrix in which there is provided at least one of the aforementioned decoders (block decoder or row decoder).

The row decoder Dz is finally provided with three voltage supply terminals to which the voltages or potentials necessary for operating the memory matrix are applied.

As is generally customary, the RAM also has a row decoder for decoding row addresses and for addressing corresponding word lines.

In the case of the invention, the third clock signal makes it possible to distinguish between column addresses which are situated on the first column address bus and are to be supplied to the column decoder subject to the first clock signal, and row addresses which are situated on the first column address bus and are to be supplied to the row decoder subject to the third clock signal.

Whereas, in other exemplary embodiments of the invention, it is possible to supply the row addresses to the row decoder RDEC via a separate row address bus, which means that a total of three address buses (namely two column address buses and a row address bus) are required, the exemplary embodiment shown in FIG. 1 advantageously has only two address buses in all (namely the two column address buses CADR 1 and CADR 2).

At a first instant t 1, the third clock signal CLK 3 in FIG. 2 is briefly at a high level, so that a row address applied to the address inputs ADR at this instant is transferred to the row decoder RDEC via the first column address bus CADR 1 and the third transfer gate T 3 .

Since the word line WL addressed initially at the instant t 1 by the row decoder RDEC remains activated for the whole time, subsequently supplying the first column address and the second column addresses to the column decoder CDEC means that a respective data item can be read from (Dr written to the memory in the manner described.