Übersetzung für "Master pulse" in Deutsch

Separate transmission pathways can be provided for relaying the master clock pulse.

In this known system, when servo-synchronisation is used the master pulse train is fed only to one of the two exchange pulse generators.

The redundant clock pulse is then removed from the bus and the slave clock pulse is synchronized to the master clock pulse.

Thus the switching state of the shift register SRS1 has been changed. Here too, the state of master flipflop 40' is transferred before the second master-clock pulse to slave flipflop 50 by the slave-clock pulse so that when the second master-clock pulse is applied to master-clock pulse line 9, simultaneously with the input of the altered bit value into shift register stage SRS1, the bit value that had originally existed there is transferred into second shift register stage SRS2 so that here too, after completed test circuit forming, the two first shift register stages of a shift register segment are in a switching state opposite with respect to each other.

The output of NAND-element 28 is equally positive since, as pointed out above, firstly no system-clock pulse is applied and secondly, in accordance with the invention, the master-clock pulse is applied at master-clock pulse line 9, said master-clock pulse being provided via inverter 33, connecting line 52 and supply line 81 as a negative input at NAND-element 26.

As before, the originally existing positive switching state in slave flipflop 50, i.e., a positive potential level, has been transferred simultaneously with the input of the test circuit forming pulse under the influence of the master-clock pulse on master-clock pulse line 9, into master flipflop 40 of the first shift register stage SRS1, to master flip-flop 40 of the second shift register stage SRS2 so that this again produces opposite switching states in the first two shift register stages SRS1 and SRS2 of the respective shift register segment.

Instead, two separately starting test circuit forming pulses are applied individually via contacts 8A and 8B which, however, cover different periods, in such a manner that the test circuit forming pulses and contact 8A is applied, as above, simultaneously with the master-clock pulse on master-clock pulse line 9, and that it can overlap it in its pulse duration both upon starting and upon decaying. As above, it should be made sure that this first test circuit forming pulse does not cover two master-clock pulses, and that the test circuit forming pulse at contact 8B overlaps two successive master-clock pulses on master-clock pulse line 9 without any further master-clock pulses being covered thereby. In the present case, for simplifying the specification of the invention, two separate terminals 8A and 8B are provided.

Test combinational circuit 5' modified with respect to the above specification has only one output which is connected to a respectively modified master flip-flop 40' of the first shift register stage SRS1 of a shift register segment, i.e., again at the respective input of its NAND-element 24 which in that case has only two inputs, i.e., a further one serving via supply line 80 to apply the master-clock pulses to master-clock pulse line 9.

Thus, a positive output is caused at NAND-element 46 so that also the input of NAND-element 24 in master flip-flop 40' of the first shift register stage SRS1 becomes positive, if it is not positive already, for providing a negative output with the simultaneous appearance of a master-clock pulse on master-clock line 9, as shown in the pulse diagram of FIG.

The two exchange pulse generators CCG' and CCG" are each servo-synchronised in pulse train frequency by means of a master pulse train M', M" having a pulse train frequency of e.g. 2.048 MHz, which is fed to the relevant exchange pulse generator CCG', CCG" from a frequency adjustment device FN', FN" which is itself supplied with a standard pulse train N of e.g. likewise 2.048 MHz.

This logic zero in the rest state of the intermediate storage control 10 is given off by an AND-gate 85, the one input of which is supplied with a logic zero from the Q-output of a flip-flop 86, since the flip-flop 86 has been reset through the OR-gate 87 either by a preceding master resetting pulse given off by the central arithmetic and run-down control unit 3 or by a resetting pulse generated by the intermediate storage control 10 itself.

The second input of the OR-gate 92 is connected with the Q-output of a flip-flop 95, which has been reset through an OR-gate 96 driving its resetting input either with the aid of a preceding master resetting pulse or through a resetting pulse generated by the intermediate storage control 10 itself so that its Q-output delivers the logic 1, which is passed on by the OR-gate 92 to the resetting inputs of the 10:1 divider 81 and of the 4-bit binary counter 82.

However, it is equally possible to transmit the master clock pulse with the help of individual connections that are patched through by essentially known methods and then to derive the master clock pulse from these connections by methods which are likewise known.

In this case the clock pulse supply unit LT2 of this link connection circuit receives its master clock pulse in the manner described above.

Master-clock pulse line 9 is applied to the input of inverter 33 which via connecting line 52 is connected to inverter 34 whose output in turn, is connected to line 80.

The operation of a thus designed shift register is performed in such a manner that upon the appearance of a shift pulse at the input of a shift register stage the bit value of the shift pulse is entered into the master flipflop under the simultaneous effect of a master clock pulse.

During time T1 substantially extending over one single period of the master-clock pulse, which means that it does not cover two master-clock pulses, a test circuit forming pulse is applied via terminal 8 simultaneously with a master-clock pulse, to master-clock pulse line 9.

However, if a test circuit forming pulse is applied there is a negative pulse at the input of NAND-element 22 so that the output of NAND-element 22 is positive, too, and that therefore simultaneously with a master-clock pulse on master-clock pulse line 9 all inputs of NAND-element 24 in master flipflop 40 are positive whose output becomes negative in responding thereto.

The slave clock pulse is then removed from the bus for system clock-pulse distribution and the redundant clock pulse is synchronized to the master clock pulse.

With the subsequent slave-clock pulse of reversed polarity the bit value is transferred to that slave flipflop whose output serves in combination with a second master-clock pulse as an input quantity for the following shift register stage.