Übersetzung für "Capacitive loading" in Deutsch

The run time is substantially lengthened in all types of multiplier, particularly by the capacitive loading owing to further adder inputs.

Since the W/L ratio of the output transistor tr cannot be made arbitrarily large compared to that of the coupling transistor ta because of the capacitive loading, according to the invention, a different approach is taken by means of a positive-feedback circuit mk to further increase the transconductance of the CMOS transconductance amplifier.

The increased (capacitive) loading of the output has a disadvantageous effect on the delay times in all logic families.

The remaining capacitive loading of the gate terminal, for example, with respect to the drain and source doping regions of the transistors 20, 21, is significantly lower than the above-mentioned parasitic capacitances.

The capacitance of the boosting capacitor 2 is calculated on the basis of capacitive voltage division between the boosting capacitor 2 and the capacitive loading connected to the output terminal 29, while taking account of the desired level of the output voltage.

The low capacitive loading effected also at the low resonant frequency can be taken into account in designing the antenna arrangement by making the entire radiator initially somewhat shorter than would have to be the case without the presence of the capacitor at the low resonant frequency.

An advantage which is obtained by the measures of the present invention is that only an insignificantly larger chip area is required for the present tri-state driver circuit in comparison to the chip area required for the known tri-state driver circuit and, further, no additional capacitive loading of the driver output is effected by the circuit of the present invention.

In most cases, a connection via the short partial bus lines will suffice here, which keeps the capacitive loading on the line drivers small and thus also keeps the propagation delays short.

An active frequency separating circuit is known (German Patent DE-PS 38 02 810) which has the advantages that, to a large extent, a deleterious capacitive loading is avoided for AM-band signals, and that the active components of FM and AM amplifiers are affected only insignificantly by signals in the respective other range.

By this means, a compensation of the capacitive loading caused by the absorbers is achieved in relation to the characteristic impedance.

Since the dissipated power of the crosspoint matrix is primarily the charging power to be exerted on the matrix lines, the overall power consumption, given reduced capacitive loading of the matrix output lines, is also reduced in addition to the charge reversal times.

Depending on the magnitude of the capacitive loading of the local bit line 10, a resulting read-out signal 14 is provided on the local bit line, which read-out signal is assessed by a read block 16 connected to the local bit line 10 as LOW or HIGH level—to be output in valid fashion—of a bit signal.

In this case, a resulting read-out signal is provided on the local bit line depending on the magnitude of the aforementioned capacitive loading of the local bit line, which read-out signal is assessed by a read block connected to the local bit line as a LOW or HIGH level—to be output in valid fashion—of a bit signal.

The disadvantage of this measure is an increased area requirement and a greater capacitive loading on the preceding amplifier stage or the connected sensor, which leads to an attenuation of the signal.

This increases the total capacitance of the capacitive loading of the bit line during the respective reading of the bit occupancy of the selected memory transistor.

Such unilateral capacitive loading to the vertical element is also possible and may be appropriate under certain conditions.

To obtain good bridging to the vertical printed conductor section 17 of the first printed conductor pattern section 14 of the front printed conductor pattern 12, the embodiment with double-ended capacitive loading of the first printed conductor pattern section 20 on the rear printed conductor pattern 13 is, therefore, preferred.

The capacitive loading thus has a similar effect to the top-loading capacitances known from the field of “normal” broadcast antenna construction, which are arranged at the top end of vertical monopole rod antennas erected on buildings, etc., but it must be considered additionally in this case that, due to the small geometric dimensions and the vicinity to the shield cover, the circuit board, the battery pack or other parts of the device, unavoidable capacitances to ground of the device occur and, in addition, the detuning by the hand of the user as mentioned occurs.

Such capacitive loading at the end of the first printed conductor pattern section leads to an improvement in the current distribution of the antenna.

In this way, what is present as reference is a memory cell in the case of which the capacitive loading of the bit line with the channel not formed is known and can be used for comparison in the differential measurement.

If, in the case of the selected local bit lines 10, the memory cell transistor is driven by a respective read potential 13 at its gate via a word line 3, a read-out operation is realized by a procedure in which a capacitive loading of the local bit line 10 dependent on the magnitude of the charge stored on the floating gate of the driven memory cell transistor is generated.

Since only the voltage swing is measured and the drain/ground capacitance is continuously effective as capacitive loading of the local bit line 10, only the effect of the first or second source/ground capacitance 8, 9 is thus measured.

During the read-out operation, a capacitive loading of the local bit line dependent on the magnitude of the charge stored on the floating gate of the driven memory cell transistor is generated.

By contrast with an adder input, the capacitive and ohmic loading by an inverter input is virtually negligible, and the structure is further simplified.