Übersetzung für "Synchronous clock" in Deutsch

The synchronous clock pulse could be distributed over a separate line network.

The invention relates to a circuit configuration for synchronous clock generation of at least two clock signals.

The remaining area (spare) in the synchronous clock I is a safety time buffer.

In this case, the bundled network access links work with a synchronous clock generator.

The acquisition and write processes of the equalizing memory G1 are thus clock-synchronous with the link changeover device LUX.

The acquisition and write processes of the equalizing memory E4 are clock-synchronous with the link changeover device LUY of the partner line group.

In a further step a clock-synchronous, frequency-selective evaluation of the received signal is carried out in each of the evaluation units.

The configuration and driving of the transmitter can be effected via a data line that is synchronous with the clock line.

It is particularly advantageous that the real-time information is supplied in real time, in other words, in a clock-synchronous manner.

Clocks that are synchronized with each other across the subsystem boundaries are an essential prerequisite for clock-synchronous recording to be carried out across the subsystems.

The invention relates to a synchronous clock generator for digital signal multiplex devices comprising a first counter whose counting period corresponds to a block length of a pulse frame and which can be set into a prescribed counter reading, comprising a block counter controlled by said first counter and comprising a logic element connected to the outputs of the counters for generating working clock signals.

Synchronous-mode operation is the most obvious mode for a clock synchronous broadband network, in which the node clocks can be derived from the already existing standard frequency distribution network.

The method according to the invention has the advantage that a clock-synchronous network can be constructed in which asychronously operated space-division-multiplex switching networks can be used in the nodes.

BACKGROUND OF THE INVENTION The invention relates to a synchronous clock generator for digital signal multiplex devices comprising a first counter whose counting period corresponds to a block length of a pulse frame and which can be set into a prescribed counter reading, comprising a block counter controlled by said first counter and comprising a logic element connected to the outputs of the counters for generating working clock signals.

Since delay times occur in the gates and the flip-flops, it is advantageous in many applications for scanning clock-synchronous processing operations to provide these two registers which restore the synchronization with the scanning clock.

Since the ON state of the gate circuit g is controlled by the low level of the clock signal cl or by the high level of the antiphase clock signal clq, the onset and duration of the pulses of the difference current i8d are synchronous with these clock-signal phases.

The source data and control data are transmitted through the ring feeder in a continuous data stream which is synchronous with a clock signal.

Through the data line the source and control data are transferred in a continuous data stream which is synchronous to a clock signal.

Master clock generator 2 contains a clock selector 5 which selects one of the received clock signals and generates a master clock synchronous to it.

The invention relates to a method for the common transmission of digital source data and control data between data sources and data sinks, which are subscribers to a communication network with a ring structure, the source data and control data being transmitted in a format which prescribes a pulsed sequence of individual bit groups of identical length in which specific bit positions are reserved in each case for source data and control data, which are transmitted in a continuous data stream synchronous with a clock signal.