Translation of "Serial transfer" in German

The converter supports a serial transfer rate from 300 to 115200 bps.

During a serial data transfer, a constant signal level, for instance HIGH, can be set.

Serial data transfer using a data bus is also possible provided that the interface module is equipped for it.

The PPP protocol 10 is located on layer 2 of the OSI protocol and serves to provide serial data transfer via selective connections.

However, the read-in process at the store can also be programmed so that, for example, it is also possible to switch temporarily as required from parallel transfer of signal sections into the signal store to serial transfer.

The P/S converter 62 produces at its output 64 pulses whose "lengths" and "distances apart" are a coded representation, in a known manner, on the principle of serial data transfer of the measured values processed by the microcomputer 40.

Another disadvantage is that, because of the serial signal transfer over the trunks as well as the multiplex lines, only a relatively small number of subscriber stations can be included in a connection.

Thus, some of the slaves may have an interface for a parallel data transfer, while each of the other slaves has an interface for a serial data transfer.

By means of this clock signal, all bits, for instance starting with the highest bit, are counted individually upon a serial transfer of digital data.

The data transmission can be performed, in particular, according to the known serial data transfer topologies, as are found, for example, in the computer engineering as well.

Upon the serial data transfer, i.e. both upon serial reading and serial writing, a clock signal SCLK (serial clock) having eight rising and eight falling edges is set and transferred together with the serial data SD.

In this case, the CAN component is designated by the reference symbol 1, the EEPROM is designated by the reference symbol 2, the connection configured for serial data transfer between the CAN component 1 and the EEPROM 2 is designated by the reference symbol SIO, and the CAN is designated by the reference symbol CAN.

The serial data transfer can be monitored in the ASIC 14 in conjunction with the first circuit part by means of a test circuit 702.

The serial data transfer can also be tested in the ASIC 14 in conjunction with the first circuit part on the basis of a local loop and with the test circuit 702.

The acknowledgement code is present in the test shift register 720 so as to be fetchable in parallel and the test circuit 702 is fashioned corresponding to a security printer mode that has been set in order to monitor the serial data transfer between the print register 15/printer head electronics 30 and the transfer shift register 710 to monitor the received bits for predetermined status change.

The second acknowledgement code is present so as to be fetchable parallel in the test shift register 720 and the test circuit 702 is fashioned corresponding to a security printer mode that has been set in order to monitor the serial data transfer between print register 15/printer head electronics 30 and the transmission shift register 710 in order to monitor the received bits for predetermined status change.

While serial transfer is taking place after connection setup, normal transfer of data and/or programs can take place on the parallel bus.

This increases the throughput of the entire system cumulatively by adding both parallel and serial transfer.

For this reason, with the high-speed bus system according to this invention, it is possible to mix modules with a serial and parallel transfer capability with modules having only a parallel transfer capability.

The "BUSY" signal mentioned earlier indicates that serial transfer is in progress and thus allows TIMEOUT supervision of all serial drivers.

This allows each module to detect whether or not it can actively initiate connection setup for a serial data transfer.

The control unit can be also fitted with a field bus communication unit, which as part of a serial data transfer system renders possible communication with an external electronic control device or, respectively, the communication between a plurality of separately arranged valve arrangements inter se.

The method according to claim 1, wherein at the start of the step of setting up the connection, a single data word is transmitted in accordance with an associated address via the serial bus for selecting a module and transferring a memory address, and thereafter an enabling signal is generated by the module to immediately enable the parallel bus so that, while serial data transfer is still taking place, the parallel bus is made ready for independent parallel data and/or program transfer.

The method according to claim 1, wherein, in the event of block transfer in accordance with a protocol exclusively via the serial bus, data are transferred over said at least one parallel bus during connection setup, said data containing the information necessary for serial data transfer such as start address and block length.

High-speed bus system comprising at least one parallel bus and at least one serial bus combined for simultaneous parallel data and/or program transfer and serial data transfer, with a logic circuitry being operatively connected to the parallel bus, said serial data transfer taking place after connection setup at the same time as said parallel data and/or program transfer is taking place on the parallel bus, and connection set up for both parallel data and/or program transfer and serial data transfer taking place using the logic circuitry of the parallel bus.

In order to solve this task, the present invention provides a high-speed bus system in which at least one parallel bus and at least one serial bus are combined for simultaneous parallel and serial data transfer with serial data transfer taking place after connection setup at the same time as normal transfer of data and/or programs takes place on the parallel bus and where connection setup for both parallel and serial data transfer takes place using the logic circuitry of the parallel bus.

Using the existing logic circuit of the parallel bus for connection setup in both parallel and serial data transfer means that only relatively little additional logic circuitry is needed to control high-speed serial transfer.

In the method according to the invention of operating a high-speed bus system, at least one parallel bus and at least one serial bus are combined with each other and the method can, for example, be carried out so that during connection setup, as described, for instance, on pages 74 and 75 of the publication mentioned in the introduction, with a single transfer or transfer of a data word under an associated address via the serial bus, after selecting an addressed module and after transferring a memory address, an enabling signal (DTACK signal) is generated by the addressed module in order to immediately enable the parallel bus so that, during serial data transfer, the parallel bus is made ready for independent parallel transfer of data that takes place at the same time.