Translation of "Redundant bit" in German

Don't you think throwing dirt on the Dodge is a bit redundant?

Sorry, that was a bit redundant.

This defect is again repaired by one of the redundant bit lines RBLi.

The particular connected word address is of no importance for reading out the redundant bit lines.

Under certain circumstances it is also possible to correct errors by use of the redundant bit words.

Aesthetically, the LG G8S ThinQ is the G8 ThinQ, which would be a bit redundant.

Analogously, the redundant bit lines 122 can be used for the blocks 104, 108 and 112 .

I think threatening to kill me is a bit redundant when we're all about to die anyway.

The invention allows a fully flexible test capability for memory cells, including redundant word and bit lines, without any additional test pad being required for the information as to whether the intention is to address a redundant or a non-redundant element.

This defect was repaired by the bit line 1 being replaced by the redundant bit line RBL 0 .

This defect is not repaired by a redundant bit line, since the defect counter X is incremented to three and has thus exceeded the limit value Y, which likewise has the value two.

The limit value Y is again fixed at the value 2, since two of the redundant bit lines RBLi are again available for programming.

These are the redundant bit lines RBL 1 and RBL 2, whose programming, as just described, has been canceled.

The first submethod is continued in an analogous manner, the programming of some of the redundant bit lines being canceled whenever the reading of the counter X exceeds the limit value Y.

The pointer P points to the third redundant line RBL 0 in the meantime, with the result that the current defect is replaced by the redundant bit line RBL 0 .

If the address AD of the memory cell MC that was checked last remains below the threshold value, the limit value Y for subsequent calling of the first submethod A 1 is decremented or incremented by 1, proceeding from the current value YS, depending on whether or not a redundant bit line RBL is no longer available (RRBL=0).

However, since in all the information input into the input/output unit is coded in the fuses and this information is decoded in the buffer and decoder, a faulty bit line in one half of the arrangement, that is to say on one side of the central bus, can be replaced with a redundant bit line on the other side of this central bus, so that all “repair opportunities” are kept open.

When a fault in a first bit line occurs in a semiconductor memory configuration having the redundant multiplexer according to the invention, then the present invention allows a first set of fuses to be burnt in order to correct this fault by the faulty bit line being replaced by a redundant bit line.

This information about faulty bit lines is stored in fuses (FUSES) 3 . This means that these fuses contain coded fuse information CFI which indicates which bit lines are faulty and need to be replaced with redundant bit lines.

This time delay is ultimately caused by the redundant bit lines in area 11 for the redundancy multiplexer 9 and in area 12 for the redundancy multiplexer 8 being driven via the entire width of the interface on both sides of the central bus 1 .

On the basis of these switch signals, the data input into the switches 14 (“Data in”) are passed on by the switches 14 in the redundancy multiplexers 8, 9 (“Data out”), in order thus to drive any redundant bit lines, for example in the area of the central bus 1, as indicated schematically in FIG.

Once the entire semiconductor memory has been tested, the identification data and the correlation plan are supplied to the automatic repair device which, while using the identification data of the correlation plan, known algorithms and further means that are known per se, replaces the word lines WL and/or groups of pairs of bit lines BL, along which defective memory cell groups (or memory cells) have been detected, with redundant word lines WLred and/or groups of pairs of redundant bit lines BLred and their redundant memory cells MCred.

The M pairs of redundant bit lines BLred in this configuration can be connected through the redundancy read amplifiers SAred and the redundancy bit switch block BKBSWred to the lines of the group databus GPDB.

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a redundant multiplexer for a semiconductor memory configuration for replacing two faulty bit lines by two redundant bit lines, in which information which is stored in fuses and relates to which bit lines are to be replaced is used to produce control and switching signals in a decoder.

When testing semiconductor memory configurations, the person carrying out the test generally has to decide to burn or to select fuses associated with a faulty bit line that is present, in order in this way to replace the faulty bit line by a redundant bit line.