Übersetzung für "Clock edge" in Deutsch

At the adder's input a tuple ai, bi appears at each rising clock edge.

At the next rising clock edge, the count value is decremented.

Thus, the D flip-flop 401 a takes over the input with a rising clock edge to the output.

Furthermore, each failing clock edge (re-)triggers the monostable flip-flop.

The next data bit DB is provided with each further rising clock edge.

Alternatively, a negative clock edge can also be interpreted as a close-switch signal.

In this case, the descending clock pulse edge may be used to scan the output signal of the unity-gain amplifier.

In this case, the falling clock edge could be used to sample the output signal of the voltage follower.

In a synchronous logic, the circuit is susceptible to disturbances by SETs only during the clock edge.

The first transition of the interpretation signal KF1 from the logic value "0" to the logic value "1," lies shortly before a rising edge of the sampling clock pulse PT (by contrast, the corresponding transition of the delayed signal KF1* at the information input D1 lies shortly after the rising clock pulse edge.

In the case of the following rising clock pulse edge, the first flip-flop 12 is, indeed, set, but is immediately again reset, because the interpretation signal KF1 disappears again.

The third transition of the interpretation signal KF1 from "0" to "1" is located before a rising edge of the sampling clock pulse PT in such a manner that the corresponding transition of the signal KF1* at the input D1 of the first flip-flop 12, which signal has been delayed in the delay element 11 by less than half a clock pulse period, takes place just barely prior to the clock pulse rising edge.

This can lead to errors in the evaluation of the flip-flop outputs after the occurrence of the triggering clock frequency edge.

As soon as a clock pulse (edge of logical "1" to logical "0") occurs the voltage of logical "1" applied to input D is taken up by the memory.

The readjustment is effected so that one edge of the symmetrical clock signal coincides with the zero crossings or extreme value of the color synchronizing signal, respectively, so that the other clock signal edge is located at 45°, 135° etc. of the color synchronizing signal.

No change of state occurs in the PDM signal pm at the instant t4 during the jittering clock-signal edge.

This is the time interval preceding and succeeding the clock pulse edge whereby the data is to be transferred into the register.

As mentioned above, the input data of the second register may not be modified in the time interval during which a clock pulse edge of the second clock signal occurs with which new data is transferred to the second register.

In the case of the following rising clock pulse edge, the first flip-flop 12 is, indeed, set, but is immediately again reset, because the interpretation signal KF1 disappears again. (KF1?1).

The output signals of the non-inverting output Q of the first D-flip-flop FF1 and of the inverting output Q of the second D-flip-flop FF2 are combined with the gate G2, so that a 1-pulse appears at the output C2 of the second gate G2 with the appearance of the logical 1 at the non-inverting output of the first D-flip-flop FF1, this 1-pulse lasting until the beginning of the second clock edge after the appearance of the pulse for code error overlaying CFE.