Übersetzung für "Clock buffer" in Deutsch

A second solution provides for a direct switching of the service signal and the interposition of the buffer clock with the inverted receive clock only during periods in which there is a threat of phase coincidence between the receive clock and the transmit clock.

The address buffer register AZR and the two flip-flops U2 and P2 are constructed as a latch, i.e. beginning with the trailing edge of the system clock, the address buffer register AZR and the two flip-flops U2 and P2 are transparent up to the leading edge of the next-successive system clock.

These several subassemblies are saved intermediately with the write clock in the buffer memory and with the higher or lower read clock in such a way that several synchronous output signals are created.

In addition, the input signals are written bit by bit with a write clock into buffer memory and read again with a read clock in order to form the synchronous output signal.

Assuming two address operations for the ALU and a single data transfer between the data memory and the buffer during one clock period, the buffer must move data across three memory cells in one cycle, i.e., one memory cell is only read from by the ALU, a second is both read from and written into by the ALU, and a third is either read from or written into by the data memory.

A crystal or oscillator should be connected to the non-compliant device either directly or via a clock buffer.

It is also important to ensure that any clock buffers do not have a minimum operating frequency.

Some clock buffers have a special control input to allow low frequency signals.

The difference in the digital values obtained for adjacent clock times is buffered in accordance with sign and value, which is proportional to the slope steepness, and thus depends on the focussing adjustment.

The buffer store 33, which is also arranged as a register and receives the auxiliary signal HS on its clock input, buffers the values produced by buffer store 32.

The clock recovery devices 51-54, without auxiliary clock generators, buffers, 55-58 and the multiplexer 59 can be combined as an integrated circuit 63.

Finally, it is also possible that the operation of the food slicing devices is synchronized such that the entire system can be operated in a clocked manner whereby buffering capacity in buffering devices 12, 13, 18, 19 can be saved.

Such an inaccuracy in the absolute clock time of the clock source is unacceptable for the real-time operation of a head end, because the data packets of the encrypted transport datastream, which are provided with a timestamp from the clock source, are buffered in the buffers of the individual transmitters either for too long and therefore cause an overflow of the buffers, or are buffered for too short a time and therefore cause a zero loading of the buffers.

If a configurable JTAG device, such as a CPLD or FPGA, is available then route the clock source through that device to the SDRAM or clock buffers to maximize test coverage as shown below.