Übersetzung für "Bit timing" in Deutsch

This simplifies recovery of the bit timing or clock and improves error control.

This setting is also referred to as bit timing.

A sort of low pass filter in the adjusting algorithm for the bit timing can minimize this effect.

FIG. 2 shows an example for the different settings of the bit timing as a function of the transmission rate.

The synchronizing unit 54 is a unit, known per se, which regenerates the bit timing BT and the packet timing PT from the signal pattern on the fiber 11 synchronously and in correct phase.

In the L state, the subordinate control 62.1 immediately sends a transmit command to the buffer storage 68 via the connection 64, whereupon the buffer storage 68 via the output amplifier 51 transmits the data contained with it to the respective empty packet in bit timing BT.

The bit timing can then be derived from an internal clock rate, with the aid of a frequency phase-locked loop or of the microcomputer, and kept in accordance with the synchronization performed.

The packets 45 are formed in such a way that every access unit 13 can be synchronized independently to the bit timing BT and the packet timing PT of the packets 45.

In this case, it is an empty packet which is to be filled immediately with the prepared data by means of modulation in bit timing BT.

The generation of bit timing CI, according to line 9, occurs by means of the first frequency divider stage FT1 which is implemented as a J-K flipflop.

For different applications, particularly for the processing of digital audio data from a CD, the data words are transmitted bit-serially with a data bit timing.

A configuration TA for clock-pulse derivation containing a second delay element V2, having a delay also corresponding to one half of a bit duration of the CMI-coded or binary signals, is provided for the generation of the bit timing for the first D flipflop DF1.

For this purpose, the D input of a second clock D flipflop DF2 is connected to the output of the first AND gate AND1, and the D input of a third D flipflop DF3, clocked with the bit timing, is connected to the output of the NOR gate.

Besides a clock input supplied with bit timing BT, counter 11 has an enable signal input EN and a load signal input LD.

As embodied herein, a signal applied to input EN causes the counting of the clock signals of bit timing BT to be interrupted, while a signal at load signal input LD permits the signals being applied to the set inputs A through N to be transferred to outputs Q.

Similarly, the falling edge of period 3F 1 is synchronized to the next rising edge of the bit timing.

It is also possible, however, that a bit timing signal of the circuit for executing the ASIC functions is converted to a nibble timing signal or a byte timing signal of the data test circuit.

Since the switching matrix operates in unclocked manner, i.e. its switching function is not based on internal bit timing and frame timing, arbitrary signals can be switched though transparently at almost any bit rate, independently of the protocol-type being used.

The switching matrix operates advantageously in unclocked manner, i.e. its switching function is not based on internal bit timing and frame timing.

One of these conditions is that all the nodes N 1 to Nn output the data they output onto the CAN bus CANBUS at the same bit rate or with the same bit timing.

A known method of avoiding phase errors is edge-based resynchronization, i.e. the bit timing of the receiver is adjusted to the data stream on receipt of each edge in the message or each bit.