Übersetzung für "Schreibzyklus" in Englisch

In the Write cycle, they are open.

Immediately following the write cycle, the read operation occurs.

With each write cycle on the processor bus, the stack reads the address.

Over the entire serial writing cycle, the parallel data bus preferably remains undriven.

In the parallel write cycle or write access in accordance with FIG.

The shortest possible write cycle generally lasts at least as long as the minimum read cycle.

Under the control of the control means ST, a write cycle in the counter reading memory ZSP follows.

With a rising CE edge this circuit is again prepared for the output state of the next writing cycle.

The write cycle is thus reduced.

The process consisting of 9 reading cycles, the reformatting, and the write cycle must still be repeated 17 times until the entire replacement circuit information is written in to all memory circuits of a memory printed circuit board or module.

The transfer switch a is illustrated in the drawing in such a manner that, in accordance with the illustrated switch position, the full memory U is currently in the write mode and its write cycle has just begun (the selection write means c has just been set to the memory location u0).

A write cycle of one of the memories extends over the duration of as many successive time slots as partial information could arrive during the time of a pulse frame.

When the picture is not frozen, the write-in cycle is used continuously but the read-out cycle is used only during the time when the compound picture appears (on the screen of television monitor 18) within the time interval per television picture.

The MOSFET 41 contacts 43,44 are preferably electrically independent from the circuits used in the writing cycle 27 and are fabricated near the barrier layer 9 in the recess 6 beneath an insulating barrier layer 9' on the substrate 7. The laterally projecting portion 45 has about half of its length connected to the mechanical component 2 and acts as a GATE electrode of the MOSFET 41.

As explained below in detail, the second control device causes per write cycle of the video storage device 4 and per read cycle of the fifo storage device 3, respectively, re-storage of a plurality of data words from said first storage device 3 into the video storage device 4; the number of data words restored can vary from case to case, as explained below.

Within a reading or writing cycle defined by such a control signal for the direction of transfer, another control signal in the form of a separate strobe signal is activated, it being conducted over a further control line of the bus system.

Upon a write access to the parallel data bus (parallel writing cycle) and thus to a slave with a parallel interface, corresponding address signals and a control signal for the type of transfer are again first set.

Also in the case of the parallel writing cycle, the clock signal for a serial data access is constant over the entire time of the cycle, for instance LOW.

New data is then written directly over the old data in one pass, without it being necessary to erase the old data first during a separate write cycle.

The strobe signal STRB differs from a parallel cycle or access by the pulse time t'2, which is determined in the serial write cycle by the length in time of a transferred byte having eight (8) bits BIT7 . . . 0.

Upon an access, and in particular a write access, to the serial data bus of the bus system (serial writing cycle), a corresponding clock signal (serial clock) is set.

In this connection, upon a serial write cycle, the serial data conducted over the serial bus system are driven by the master.

To this end, it may also be that when the printing device 101 is activated, the printing device 132 is heated to a pre-set temperature producing a fast print cycle as the information carrier 104 is fed out.