Übersetzung für "Reset the clock" in Deutsch

Try to get into the main operating system and reset the internal clock.

Someone has reset the clock.

Your login will be enough to reset the 12-month clock.

The reset also overrides the clock signals and simultaneous setting and resetting are not permitted.

After a predetermined number of clocks of a reset clock, the respective read-out lines are deactivated again.

If there is a change in the required carrier frequency range, the FIR filter characteristic is reset accordingly via the clock frequency.

Circumstances denied us that initial opportunity, but I am hoping today, with your permission, to reset the clock.

Since the m clock pulse signals of an m-phase CCD can be derived from the frequency fA '=mfA, no large additional expense arises for generating the reset clock pulse and the scanning or sampling clock pulse.

Of course, the decoders would require a multiplicity of address inputs, in place of the reset and clock inputs provided for the shift registers.

The first control device 5 is set to an initial condition by means of the first blank signal BL(1) so as to reset a zeroth selection signal SEL0 and set a first selection signal SEL1 (with circuit dependent delay) in response to the appearance of a first clock pulse CLK(1), the first selection signal being reset and the second selection signal SEL2 being set in response to the second clock pulse CLK(2), etc., and, subsequently, the third selection signal SEL3 is reset and the fifo write signal WF is set after the third pulse, whereupon the third selection signal is reset after the fourth clock pulse and the fifo write signal is reset after the subsequently following first clock.

The flip-flop 7, if it is a bistable circuit, will either be reset by the next clock pulse, whereby at the same time the transfer of the current count state is put into the buffer store, or if the flip-flop 7 is a monoflop, the resetting is produced automatically by the monoflop when it returns to its normal state.

When all registers are occupied, however, even if only briefly, for example with the transfer of the data word E, then the synchronizing flip-flop SYN-FF is instantaneously reset and the next clock pulse in the timing pattern f1 of the outputting system does not lead to a request pulse, for example at points in time X and Y, since the synchronizing flip-flop SYN-FF must still be reset.

As there is a very high probability that, after a power-on reset, the clock time in the external apparatus 2 is wrong, immediate time synchronization is provided for that situation.

During this synchronization reset, the clock-signal generator continues to oscillate, so that the time period necessary for synchronization is very short.

The arrival of the trigger signal then results in the synchronization reset, during which the clock-signal generator of the microprocessor continues to oscillate.

An apparatus as claimed in claim 4, wherein the reset clock signal has a frequency which is higher than a cycling frequency with which the rows are activated successively during the read process.

At the same time, the register R2, which is connected after the adder A1 and forms an accumulator therewith, is reset by the clock signal T1.

If no pulse arrives from the outputs 9 and 10 of the phase discriminator, the reset input receives a reset signal and the clock pulses at the clock pulse input of the counter 22 are ineffective.

The third clock sequence T3 is applied to the count instruction input ZB of the counter Z2 and the reset clock sequence RT is connected to the reset input R of the second counter Z2.

The reset clock sequence RT is respectively applied to the set instruction inputs S of the fourth delay flip-flop F4 and the fifth delay flop F5 and a potential corresponding to the logical "1" level is respectively connected to the reset instruction inputs R of the fourth delay flip-flop F4 and the fifth delay flip-flop F5, i.e. these inputs are connected inactive.

The reset clock sequence RT, which likewise comprises a pulse repetition frequency of 16 kHz comprises a short negative pulse following, for example, each rising signal edge in the second clock sequence T2.