Übersetzung für "Instruction decoder" in Deutsch

The control circuit Con can, for example, be formed by the instruction decoder of the microcomputer or microprocessor MC.

The data path controller is composed of the instruction register BR, of the instruction counter BZ, of the address decoder ADRDEC and of the instruction decoder BEFDEC.

The command data CMDx are then forwarded by the instruction decoder ID to the left and right; namely to the units RR, E, DT, DI, RW or SC arranged in the pipeline.

Such an array is well known, and normally includes, inter alia, an accumulator register which stores one of the operands to be manipulated by the ALU, a program counter, an instruction register and decoder, as well as an address register.

The instruction decoder id produces M control signals ic, such as the circuit-related ALU instructions, which perform an addition.

The instruction decoder id is connected via a third input to the ALU u so that the requested program segment can also be controlled by an ALU operation.

The control signals may be transmitted to the transducer device more reliably if the control signal includes an encoded data sequence, which is associated with a certain instruction in a decoder following the detector circuit.

Since it is assumed that there has still been no event gate 19 is switched also via inverter 16 and control input 46, so that the instruction reaches operation decoder 7 as an effective operation EOP2.

In a preferred embodiment, the multi-core architecture is formed by a microprocessor on a chip with several computing engines, wherein in this context the term computing engine refers to an at least basically complete central processing unit (CPU), which comprises its own arithmetic logic unit, its own register, its own instruction decoder and/or its own floating point unit.

A processor generally includes registers, an arithmetic-logic unit, an instruction decoder that translates machine instructions into usable instructions and, if so required, breaks the machine instructions down into individual processing steps, as well as a control unit that controls the remaining components of the processor by setting suitable signals.

The components include a sequence controller SC, an instruction decoder ID, a register read unit RR, an execute unit E, a debug interface unit DI that may be deployed in a data transfer unit DT, a register write unit RW, an input and output unit I/O as well as a register file RF.

The four outputs of instruction register 18 are connected to an instruction decoder 19, which has first, second and third instruction outputs 20, 21 and 22 .

The interface circuit 3 thus has an instruction decoder which reacts to the special destination address by writing the contents of the receive buffer 9 directly into the control and status registers 11.

An example is a first bus system with an address bus between the program counter PCT and the opcode memory OP and a data bus between the opcode memory OP and the instruction decoder ID, as well as a further bus system with an address bus and a data bus between the data transfer unit DT and the input and output unit I. With the aid of a further bus system, the command bus, each processing unit in the pipeline of the RISC processor is informed of the address and of the data type of the current data (load, store or OP Code).

The instruction decoder id further produces task request signals which are applied over the 16-bit task request bus tb to the scheduler sc. Thus, the desired program segment is also selectable via the program.

The core of the design — the main processor — was termed the General Data Processor (GDP) and built as two integrated circuits: one (the 43201) to fetch and decode instructions, the other (the 43202) to execute them.

Upon detecting that the instruction contained in the instruction buffer 10 is aHVVA instruction, the instruction decoding hardware 12 next generates control signals, indicated symbolically by the lines 112 and 212, which cause the two operands to be fetched from main storage in accordance with the base register and displacements specified in the instruction.

Upon detecting that the instruction contained in instruction buffer 10 is an IPDE instruction, the instruction decoding hardware 12 next generates control signals, indicated symbolically by the line 112, which cause the operand to be fetched from main storage.

An instruction word which is read out of the buffer memory arrangement 20 to 23 reaches an instruction decoding element 33 and is then interpreted by a microprogram 34 which delivers activating variables to its outputs in a manner known in itself.

This for example it can be seen that the decoded instruction word DO causes the microaccess in line ZOO of the microprogram, whereby in turn the execution EXOO occurs during the step 6.

The program-controlled unit according to claim 15, wherein at least one of said multiplexers is assigned to each instruction-execution unit, and wherein output terminals of said multiplexers assigned to an instruction-execution unit are connected to input terminals of the instruction-decoding unit assigned to the respective instruction-execution unit.

In contrast, the implementation of a data-controlled, conditional command with a single program command allows access to all implemented data memories, because the relevant desired instruction is decoded in dependence upon the data, for example, dependent on the contents of a processor register as a pointer.

This has the advantage that no tables are required in the decoder and the characteristic curve of the quantization can be adapted to the current statistics in the decoder without having to instruct the decoder.