Übersetzung für "Taktausgang" in Englisch

The output of the four-element divider FT1', again, is connected to the clock pulse output AT.

One output of the second trigger stage K22 corresponds to the clock pulse output AT.

A clock signal is emitted from the processor 2 at a clock output 10 .

The clock driver 87 has a clock output 88 .

It is connected with an optional periodic output 21 of circuit 2.

The buffer output is separated from the clock output and from the data connection.

The system clock T is applied through a clock input TE and passed on through a clock output TA.

The clock output 19 is connected directly and permanently to the output of the first comparing system 17 .

Line A of FIG. 3 depicts the series of clock pulses produced at the clock-signal output 11 of second station 4.

The clock pulse output AT of the assignment device is connected to the four clock pulse inputs of the shift registers SR1--SR4 and to the clock pulse inputs of the channel devices KE1--KE4.

The level converter circuit PU is connected to the input of the fourth inverter stage I4 or, respectively, to the clock input ?E, to the ground GND, to the first reference potential VDD and to the second, generated reference potential Vss and further has its clock output ?A connected to the two gate terminals of the ninth n-channel field effect transistor N9 and of the seventeenth p-channel field effect transistor P17.

For driving the n-channel field effect transistors N1 through N4 and N8 through N11, the gate terminals are to be connected to the output of the third inverter stage I3 or, respectively, to the clock output ?A of the level converter.

The indicator lights 208 and 209 can be connected, as shown in FIG. 1, optionally via a manually switchable three-way switch 21 (direction signalling switch) having a neutral center position to the pulse output of a flasher pulse generator 214.

Given this constellation, only the amplified clock CLK2 is connected through via the NOR gate 33 and the NOR gate 38 to the clock output 21 as an adapted clock CLK and to the clocked input of the D-flip-flop 19 (FIG. 1).

If, due to extremely short delay times is the delay units 3-6, no status changes recognized and all clocked clocks Ql-Qn have a logical state of "L", then the amplified inverted clock CLKNn is connected through to the clock output 21 via the NOR gates 30 and 38.

Start/stop oscillator 36 contains a clock output 41, which is connected with a clock input 42 of shift register 34 as well as a clock input 43 of a binary counter 44 by means of respective lines.

By means of a customary, manually switchable three-way switch 113 (direction signalling switch) having a neutral center position, the right or left-hand indicator lights of towing vehicle 101 and trailer 102 can be optionally connected to the pulse output of a flasher pulse generator 114.

If the clocked clock Q2 and the inverted clocked clock QN3 had logical states of "H" and the clocked clock Q3 and the inverted clocked clock QN2 each have the states of logical "L", the inverted amplified clock CLKN2 would have been connected through to the clock output 21.

The input 3E of the flasher control unit 3 can be connected to the output 3A via a switch contact 7K of a relay 7, the relay 7 being clocked by a switching transistor 8 and a clock output 6A of the load-dependent clock generator. Clocking occurs when the potential is drawn to ground at the output 3A by actuating the driving direction indicator switch FB1 or the second contact K2 of the hazard warning switch WB1 via the low impedance light sources 1.

The processor clock from the clock output 10 is divided in the example in the ratio 8:1 (this division ratio does not have any necessary relationship to the standard representation of messages in the form of bytes which each comprise 8 bits) by a clock divider 14 .

The output signal of NAND 1 is fed via a delay member 3 and an inverter IN 1 to a clock output for the signal CLKn.

The output signal of the clock module PLL 2 is made available at the clock output CLO as a reference clock signal CS for a connected network element or a network node.

The electronic control device as defined in claim 14, wherein the second timing selection device (ZT2) includes a second AND element having an output and two inputs, wherein one of the two inputs of the second AND element is connected to the multiplexed clock output of the second multiplexer (MUX2) and a second selection signal (AS2) for selecting clock timing is fed to another of the two inputs of the second AND element, and the output of the second AND element is connected to the comparator (K).

The second demodulator DEM 10 is connected to a second decoding circuit DEC 10, whose data output is connected to the second input of the first OR circuit OR 1 and whose clock output is connected to the second input of the second OR circuit OR 2 .

By the clock pulse regeneration unit 73 the clock pulse is passed in distributed manner to MLBS generator 4, clock pulse divider 18, and to a clock pulse output 74 .