Übersetzung für "Hochzählen" in Englisch

I assume you've counted 'em up by now.

After completely counting up in the counter 18, a carry-out (CO) signal is emitted each time.

In this error-free state, therefore, the counter 38 cannot count.

The result is that the counter can continue to count.

Incrementing an 8-byte counter obviously takes longer than incrementing a 4-byte one.

This is implemented by incrementing various counters.

The spring 22 is tensioned on counting up the hole number.

Both displayed counters of the left wheel (1) must now count up.

Incrementation in the form otherwise customary is then performed from the set value, for example.

Of course, any other number amounts and a special 1-element can be used for incrementing the counters.

Incrementing the PC doesn't work, because CAR_IN_L signal is failing.

Thus, when forward counting, the signalling device is switched on when number 1 is reached, while the signalling device is switched off again upon reaching zero during backward counting.

When the travel distance FW is shorter than twice the accelerating distance BS, the incrementation of the memory cells F1-F8 is interrupted at half the travel distance F4 and is again reversed.

There is no operation of the counter Z2 during a pulse III of the first reference signal RD (i.e., time beginning at instant T5 and ending at instant T6). Thus, at the beginning of a pause IV of the first reference signal RD, the second counter Z2 is activated again (and may this time, in the exemplified embodiment, count in the negative counting direction) incrementing until the time T7 and then decrementing again until the time T8 (i.e., until the end of the pulse duration IV of the first reference signal RD).

Thus, by means not shown, in particular by heart cams, a resetting of the roller-type counter takes place by the same stepping motor as also effects the counting of the roller-type counter in a movement phase.

With the customary organization of a multi-decade counter and storage, a lower decade will, upon incrementation, change the values of its positions more frequently than the positions of the next higher decade will change.

As soon as the upward counting operation exceeds a time interval of 1.5 seconds, a comparator 21 issues an output signal, to the end that the long-time correction factors LZn are equalled to the short-time correction factor KZn in this working cycle.

Since the offset registers 1 - 4 are preferably freely programmable, they can be used to implement both simple address changes (successive incrementing) and address jumps at high clock frequency in a very flexible manner.

Up-counting of the P counter takes place in accordance with the clock frequency of clock signal CLK VCO, with the clock frequency in turn being dependent on the difference between measurement voltage V M and reference voltage Vref.

In both of these case, the pulse formed by the counter enable signal CET will usually be located outside of the time window and synchronization cantherefore not occur until after the second counter C2 has counted up.

When the controller 17 is switched on again, the counter contained in 38 is set to zero by means of a voltage pulse via the capacitor 46 at the input 12 of the IC 38 and the counting up begins in the counter from the beginning.